| A low-energy chip-set for wireless intercom |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 40th annual Design Automation Conference
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Anaheim, CA, USA
SESSION: Energy-aware system design
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Pages: 916 - 919
Year of Publication: 2003
ISBN:1-58113-688-9
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Downloads (6 Weeks): 10, Downloads (12 Months): 30, Citation Count: 0
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ABSTRACT
A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the protocol stack. Combined, the chips consume 13 mW on average when three nodes are connected to the network. A high-level design methodology was used to define the protocol stack and communication algorithms, select architectures, and minimize energy.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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W. R. Davis, et.al., "A Design Environment for High Throughput, Low Power Dedicated Signal Processing Systems," IEEE JSSC, vol. 37, no. 3, pp. 420--431, March 2002.
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D. Wingard. "On-chip Networks: the Secret to High-Performance Communication SoCs, Flexible Platforms. Integrated Communications Design, August 2000.
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D.G.-W. Yee, "A design methodology for highly-integrated low-power receivers for wireless communications," Ph.D. dissertation, UC Berkeley, Department of EECS, Berkeley, CA 2001.
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"Information Technology - Open Systems Interconnection - Basic Reference Model," International Organization for Standardization (ISO). Standard number ISO/IEC 7498--1:1994, 1994.
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