Exploring regular fabrics to optimize the performance-cost trade-off

ABSTRACT

While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.

REFERENCES

• 1: M. Palusinski, A. J. Strojwas and W. Maly, "Regularity in Physical Design", GSRC Workshop, Las Vegas, NV, June 17--18, 2001.
• 2: Paul S. Zuchowski , Christopher B. Reynolds , Richard J. Grupp , Shelly G. Davis , Brendan Cremen , Bill Troxel, A hybrid ASIC and FPGA architecture, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.187-194, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774600]
• 3: L. Pileggi, H. Schmit, J. Shah, Y. Tong, C. Patel, V. Chandra, "A Via Patterned Gate Array (VPGA)," Technical Reports Series of the CMU Center for Silicon System Implementation, No. CSSI 02-15, Mar 2002.
• 4: K.Y. Tong, V. Kheterpal, V. Rovner, L. Pileggi, H. Schmit, R. Puri, "Regular Logic Fabrics for a Via Patterned Gate Array (VPGA)," submitted to CICC 2003.
• 5: A. Koorapaty, L. Pileggi, and H. Schmit, Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics, Submitted to Int'l Conf. on Field Programmable Logic and Applications, Sept. 2003.
• 6: S. Rovner, "Design for Manufacturability of Via Programmable Gate Array Fabrics," MS Thesis Report, Carnegie Mellon University, May 2003.
• 7: Z. Or-Bach, Z. Wurman, R. Zeman, L. Cooke, "Customizable and programmable cell array," US Patent 6,331,790, 18 Dec 2001.
• 8: Chetan Patel , Anthony Cozzie , Herman Schmit , Larry Pileggi, An architectural exploration of via patterned gate arrays, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA [doi>10.1145/640000.640039]
• 9: Paul Chow , Soon Ong Seo , Jonathan Rose , Kevin Chung , Gerard Páez-Monzón , Immanuel Rahardja, The design of a SRAM-based field-programmable gate array—part II: circuit design and layout, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.3, p.321-330, Sept. 1999 [doi>10.1109/92.784093]
• 10: Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277071]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies; VLSI (very large scale integration)

General Terms:
Design, Economics, Performance, Reliability

Keywords:
cost, integrated circuits, performance, regularity