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ABSTRACT

We present a method for decomposing a high-level program description of a circuit into a system of concurrent modules that can each be implemented as asynchronous pre-charge half-buffer pipeline stages (the circuits used in the asynchronous R3000 MIPS microprocessor). We apply it to designing the instruction fetch of an asynchronous 8051 microcontroller, with promising results. We discuss new clustering algorithms that will improve the performance figures further.

REFERENCES

• 1: Alain J. Martin, Programming in VLSI: from communicating processes to delay-insensitive circuits, Developments in concurrency and communication, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1991
• 2: C.G. Wong and A.J.Martin. "Data-driven Process Decomposition For the Synthesis of Asynchronous Circuits," Proc. ICECS, 2001.
• 3: S.M. Burns and A.J. Martin. "Synthesis of Self-Timed Circuits by Program Transformation," In G.J. Milne, ed., The Fusion of Hardware Design and Verification, North-Holland, 1988.
• 4: A. Bardsley and D.A. Edwards. "The Balsa Asynchronous Circuit Synthesis System," Forum on Design Languages, 2000.
• 5: C.H. van Berkel and R.W.J.J. Saeijs. "Compilation of Communicating Processes Into Delay-Insensitive Circuits," Proc. ICCD, pp. 157--162, 1988.
• 6: J. Cortadella, M. Kishinevsky et al. "Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers," IEICE Trans. Information and Systems, Vol. E80-D, No. 3, pp. 315--325, March 1997.
• 7: R.M. Fuhrer, S.M. Nowick et al. "MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst Mode Asynchronous Machines," Columbia University CS Tech Report CUCS-020-99, 1999.
• 8: Alain J. Martin , Andrew Lines , Rajit Manohar , Mika Nystroem , Paul Penzes , Robert Southworth , Uri Cummings, The Design of an Asynchronous MIPS R3000 Microprocessor, Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), p.164, September 15-16, 1997
• 9: Alain J. Martin , Mika Nyström , Karl Papadantonakis , Paul I. Pénzes , Piyush Prakash , Catherine G. Wong , Jonathan Chang , Kevin S. Ko , Benjamin Lee , Elaine Ou , James Pugh , Eino-Ville Talvala , James T. Tong , Ahmet Tura, The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller, Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems, p.14, May 12-15, 2003
• 10: Hans van Gageldonk , Kees van Berkel , Ad Peeters , Daniel Baumann , Daniel Gloor , Gerhard Stegmann, An Asynchronous Low-Power 80C51 Microcontroller, Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems, p.0096, March 30-April 02, 1998
• 11: Alain J. Martin , Mika Nyström , Paul I. Pénzes, ET²: a metric for time and energy efficiency of computation, Power aware computing, Kluwer Academic Publishers, Norwell, MA, 2002
• 12: Rajit Manohar , Alain J. Martin, Slack Elasticity in Concurrent Computing, Proceedings of the Mathematics of Program Construction, p.272-285, June 15-17, 1998
• 13: P. Pénzes , A. Martin, An Energy Estimation Method for Asynchronous Circuits with Application to an Asynchronous Microprocessor, Proceedings of the conference on Design, automation and test in Europe, p.640, March 04-08, 2002
• 14: C. Leiserson, F. Rose, and J. Saxe. "Optimizing Synchronous Circuitry by Retiming," 3rd Caltech Conference on VLSI, 1993.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Automatic synthesis

General Terms:
Design

Keywords:
asynchronous VLSI, high-level synthesis