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System-on-chip beyond the nanometer wall
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents
Anaheim, CA, USA
SESSION: How application/technology evolutions will shape classical EDA? table of contents
Pages: 419 - 424  
Year of Publication: 2003
ISBN:1-58113-688-9
Authors
Philippe Magarshack  Central R&D, STMicroelectronics, Crolles cedex, France
Pierre G. Paulin  Central R&D, STMicroelectronics, Ottawa, ON, Canada
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 13,   Downloads (12 Months): 66,   Citation Count: 23
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ABSTRACT

In this paper, we analyze the emerging trends in the design of complex Systems-on-a-Chip for nanometer-scale semiconductor technologies and their impact on design automation requirements, from the perspective of a broad range SoC supplier.We present our vision of some of the key changes that will emerge in the next five years. This vision is characterized by two major paradigm changes. The first is that SoC design will become divided into four mostly non-overlapping distinct abstraction levels. Very different competences and design automation tools will be needed at each level.The second paradigm change is the emergence of domain-specific S/W programmable SoC platforms consisting of large, heterogeneous sets of embedded processors. These will be complemented by embedded reconfigurable hardware and networks-on-chip. A key enabler for the effective us of these flexible SoC platforms, is a high-level parallel programming model supporting automatic specification-to-platform mapping.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. G. Paulin, "StepNP: A Driver for Multi-processor SoC tools", Presentation at the Multi-Processor SoC Seminar, Chamonix, July 2003. See http://tima.imag.fr/mpsoc.
 
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M. Borgatti et al, "A Multi-Context 6.4Gbps/Channel On-Chip Communication Network using 0.18um Flash-EEPROM Switches and Elastic Interconnects", Proc. of ISSC, San Francisco, Feb. 2003.
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M. Pasotti et al, "An Application Specific Embeddable Flash Memory System for Non-Volatile Storage of Code, Data and Bit-Streams for Embedded FPGA Configurations", Proc. of Symposium on VLSI Circuits, Kyoto, June 2003.
 
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A. Clouard et al., "Towards Bridging the Gap between SoC Transactional and Cycle-Accurate Levels," Proc. Design, Automation, and Test in Europe-Designer Forum, 2002, pp. 22--29.
 
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See OCP-IP web site: http://www.ocpip.org.
 
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P. G. Paulin, "Trends and Requirements for Network Processor SoC Tools", Presentation at Multi-Processor SoC Seminar, Pizay, June 2002. See http://tima.imag.fr/mpsoc/2002/slides/paulin02.pdf

CITED BY  23

Collaborative Colleagues:
Philippe Magarshack: colleagues
Pierre G. Paulin: colleagues