| System-on-chip beyond the nanometer wall |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 40th annual Design Automation Conference
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Anaheim, CA, USA
SESSION: How application/technology evolutions will shape classical EDA?
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Pages: 419 - 424
Year of Publication: 2003
ISBN:1-58113-688-9
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Downloads (6 Weeks): 13, Downloads (12 Months): 66, Citation Count: 23
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ABSTRACT
In this paper, we analyze the emerging trends in the design of complex Systems-on-a-Chip for nanometer-scale semiconductor technologies and their impact on design automation requirements, from the perspective of a broad range SoC supplier.We present our vision of some of the key changes that will emerge in the next five years. This vision is characterized by two major paradigm changes. The first is that SoC design will become divided into four mostly non-overlapping distinct abstraction levels. Very different competences and design automation tools will be needed at each level.The second paradigm change is the emergence of domain-specific S/W programmable SoC platforms consisting of large, heterogeneous sets of embedded processors. These will be complemented by embedded reconfigurable hardware and networks-on-chip. A key enabler for the effective us of these flexible SoC platforms, is a high-level parallel programming model supporting automatic specification-to-platform mapping.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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P. G. Paulin, "StepNP: A Driver for Multi-processor SoC tools", Presentation at the Multi-Processor SoC Seminar, Chamonix, July 2003. See http://tima.imag.fr/mpsoc.
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M. Borgatti et al, "A Multi-Context 6.4Gbps/Channel On-Chip Communication Network using 0.18um Flash-EEPROM Switches and Elastic Interconnects", Proc. of ISSC, San Francisco, Feb. 2003.
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M. Borgatti , L. Calì , G. De Sandre , B. Forêt , D. Iezzi , F. Lertora , G. Muzzi , M. Pasotti , M. Poles , P. L. Rolandi, A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
[doi> 10.1145/775832.776007]
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M. Pasotti et al, "An Application Specific Embeddable Flash Memory System for Non-Volatile Storage of Code, Data and Bit-Streams for Embedded FPGA Configurations", Proc. of Symposium on VLSI Circuits, Kyoto, June 2003.
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A. Clouard et al., "Towards Bridging the Gap between SoC Transactional and Cycle-Accurate Levels," Proc. Design, Automation, and Test in Europe-Designer Forum, 2002, pp. 22--29.
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Adrijean Adriahantenaina , Herve Charlery , Alain Greiner , Laurent Mortiez , Cesar Albenes Zeferino, SPIN: A Scalable, Packet Switched, On-Chip Micro-Network, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20070, March 03-07, 2003
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Naresh Soni , Nick Richardson , Lun-Bin Huang , Suresh Rajgopal , George Vlantis, NPSE: A High Performance Network Packet Search Engine, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20074, March 03-07, 2003
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Alain Clouard , Kshitiz Jain , Frank Ghenassia , Laurent Maillet-Contoz , Jean-Philippe Strassen, Using transactional level models in a SoC design flow, SystemC: methodologies and applications, Kluwer Academic Publishers, Norwell, MA, 2003
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See OCP-IP web site: http://www.ocpip.org.
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P. G. Paulin, "Trends and Requirements for Network Processor SoC Tools", Presentation at Multi-Processor SoC Seminar, Pizay, June 2002. See http://tima.imag.fr/mpsoc/2002/slides/paulin02.pdf
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CITED BY 23
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Cristian Grecu , Partha Pratim Pande , André Ivanov , Res Saleh, Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
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Andreas Wieferink , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Tom Michiels , Achim Nohl , Tim Kogel, Retargetable generation of TLM bus interfaces for MP-SoC platforms, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
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Giovanni Beltrame , Gianluca Palermo , Donatella Sciuto , Cristina Silvano, Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems, September 22-25, 2004, Washington DC, USA
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Pierre G. Paulin , Chuck Pilkington , Michel Langevin , Essaid Bensoudane , Gabriela Nicolescu, Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 08-10, 2004, Stockholm, Sweden
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Anish Muttreja , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha, Hybrid simulation for embedded software energy estimation, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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Partha Pratim Pande , Cristian Grecu , Andre Ivanov , Resve Saleh , Giovanni De Micheli, Design, Synthesis, and Test of Networks on Chips, IEEE Design & Test, v.22 n.5, p.404-413, September 2005
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Partha Pratim Pande , Cristian Grecu , Andre Ivanov , Resve Saleh , Giovanni De Micheli, Design, Synthesis, and Test of Networks on Chips, IEEE Design & Test, v.22 n.5, p.404-413, September 2005
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Pierre G. Paulin , Chuck Pilkington , Michel Langevin , Essaid Bensoudane , Olivier Benny , Damien Lyonnard , Bruno Lavigueur , David Lo, Distributed object models for multi-processor SoC's, with application to low-power multimedia wireless systems, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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Torsten Kempf , Malte Doerper , R. Leupers , G. Ascheid , H. Meyr , Tim Kogel , Bart Vanthournout, A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms, Proceedings of the conference on Design, Automation and Test in Europe, p.876-881, March 07-11, 2005
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Pierre G. Paulin , Chuck Pilkington , Essaid Bensoudane , Michel Langevin , Damien Lyonnard, Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding, Proceedings of the conference on Design, automation and test in Europe, p.30058, February 16-20, 2004
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Andreas Wieferink , Tim Kogel , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Gunnar Braun , Achim Nohl, A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms, Proceedings of the conference on Design, automation and test in Europe, p.21256, February 16-20, 2004
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