| Schedulers as model-based design elements in programmable heterogeneous multiprocessors |
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Annual ACM IEEE Design Automation Conference
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Proceedings of the 40th annual Design Automation Conference
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Anaheim, CA, USA
SESSION: Modeling issues in the design of embedded systems
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Pages: 408 - 411
Year of Publication: 2003
ISBN:1-58113-688-9
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Authors
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JoAnn M. Paul
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Carnegie Mellon University, Pittsburgh, PA
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Alex Bobrek
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Carnegie Mellon University, Pittsburgh, PA
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Jeffrey E. Nelson
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Carnegie Mellon University, Pittsburgh, PA
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Joshua J. Pieper
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Carnegie Mellon University, Pittsburgh, PA
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Donald E. Thomas
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Carnegie Mellon University, Pittsburgh, PA
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Downloads (6 Weeks): 7, Downloads (12 Months): 25, Citation Count: 10
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ABSTRACT
As System On a Chip (SoC) designs become more like Programmable Heterogeneous Multiprocessors (PHMs), the highest levels of design will place emphasis on the custom design of elements that were traditionally associated with systems in the large. We motivate how schedulers that make dynamic, data-dependent decisions at run-time will be key design elements in PHM SoCs. Starting from a fundamental model, the role schedulers play in PHMs is developed. Model-based scheduling is introduced as an approach to designing schedulers that optimize a PHM's performance. Due to the complexity of the PHM design space, convergence on optimal design requires high-level modeling and simulation. In model-based scheduling, high-level models of scheduling decisions result in actual design elements that appear in real systems. Experiments for a simple two-processor PHM that does a mix of image and text compression are included. Results show the effectiveness of model-based scheduling.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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C.L. Seitz. "System Timing." Introduction to VLSI Systems. C. Mead, L. Conway. Reading, MA: Addison-Wesley, 1980.
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Andrew S. Cassidy , JoAnn M. Paul , Donald E. Thomas, Layered, Multi-Threaded, High-Level Performance Design, Proceedings of the conference on Design, Automation and Test in Europe, p.10954, March 03-07, 2003
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Ferid Gharsalli , Samy Meftali , Frédéric Rousseau , Ahmed A. Jerraya, Automatic generation of embedded memory wrapper for multiprocessor SoC, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
[doi> 10.1145/513918.514070]
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CITED BY 10
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Youngchul Cho , Sungjoo Yoo , Kiyoung Choi , Nacer-Eddine Zergainoh , Ahmed Amine Jerraya, Scheduler implementation in MP SoC design, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
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Brett H. Meyer , Joshua J. Pieper , JoAnn M. Paul , Jeffrey E. Nelson , Sean M. Pieper , Anthony G. Rowe, Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors, IEEE Transactions on Computers, v.54 n.6, p.684-697, June 2005
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Torsten Kempf , Kingshuk Karuri , Stefan Wallentowitz , Gerd Ascheid , Rainer Leupers , Heinrich Meyr, A SW performance estimation framework for early system-level-design using fine-grained instrumentation, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
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Torsten Kempf , Malte Doerper , R. Leupers , G. Ascheid , H. Meyr , Tim Kogel , Bart Vanthournout, A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms, Proceedings of the conference on Design, Automation and Test in Europe, p.876-881, March 07-11, 2005
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Alex Bobrek , Joshua J. Pieper , Jeffrey E. Nelson , JoAnn M. Paul , Donald E. Thomas, Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach, Proceedings of the conference on Design, automation and test in Europe, p.21144, February 16-20, 2004
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