Blade and razor: cell and interconnect delay analysis using current-based models

ABSTRACT

In order to adequately account for nanometer effects during timing analysis, archaic standard cell models must be replaced. Simplifying assumptions used during characterization, such as nearly linear voltage inputs or lumped-capacitance loads, are no longer valid. Signal integrity analysis further complicates the characterization process because the typical voltage waveform used during characterization does not contain a noise component. This paper introduces two new technologies for standard cell and interconnect timing analysis: Blade and Razor. Blade is a novel cell model and runtime engine based on current flow. Razor is the accompanying interconnect model. Both Blade and Razor produce and consume arbitrary voltage waveforms with near-SPICE accuracy at speeds tens of thousands of times faster than SPICE.

REFERENCES

• 1: F. Dartu, CMOS gate delay models for general RLC loading, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.224, October 12-15, 1997
• 2: J. Bracken, V. Raghavan, and R. Rohrer. Interconnect simulation with asymptotic waveform evaluation. In IEEE Transactions on Circuits and Systems, volume 39, pages 869--878, 1992.
• 3: John F. Croix , D. F. Wong, A fast and accurate technique to optimize characterization tables for logic synthesis, Proceedings of the 34th annual conference on Design automation, p.337-340, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266132]
• 4: F. Dartu, N. Menezes, and L. T. Pileggi. Performance computation for precharacterized CMOS gates with RC loads. IEEE Transactions on CAD, pages 544--553, May 1996.
• 5: Florentin Dartu , Noel Menezes , Jessica Qian , Lawrence T. Pillage, A gate-delay model for high-speed CMOS circuits, Proceedings of the 31st annual conference on Design automation, p.576-580, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196562]
• 6: M. Hafed, M. Oulmane, and N. C. Rumin. Delay and current estimation in a CMOS inverter with a RC load. In IEEE Transactions on CAD, volume~20, pages 80--89, January 2001.
• 7: Alexander Korshak, An Effective Current Source Cell Model for VDSM Delay Calculation, Proceedings of the 2nd International Symposium on Quality Electronic Design, p.296, March 26-28, 2001
• 8: Ying Liu , Lawrence T. Pileggi , Andrzej J. Strojwas, ftd: an exact frequency to time domain conversion for reduced order RLC interconnect models, Proceedings of the 35th annual conference on Design automation, p.469-472, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277174]
• 9: M. J. Maron. Numerical Analysis: A Practical Approach. Macmillan Publishing Co., Inc., 1982.
• 10: L. W. Nagel. A Computer Program to Simulate Semiconductor Circuits. PhD thesis, University of California, Berkeley, May 1975.
• 11: L. T. Pillage and R. A. Rohrer. Asymptotic waveform evaluation for timing analysis. In IEEE Transactions on CAD, volume~9, pages 352--366, 1990.
• 12: C. L. Ratzlaff and L. T. Pillage. RICE: Rapid interconnect circuit evaluation using AWE. In IEEE Transactions on CAD, pages 763--776, 1994.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Simulation

General Terms:
Algorithms, Design, Measurement, Performance

Keywords:
blade, cell model, current-based model, interconnect model, razor, recursive convolution, timing analysis