An effective capacitance based driver output model for on-chip RLC interconnects

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An effective capacitance based driver output model for on-chip RLC interconnects

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents

Anaheim, CA, USA

SESSION: Delay and noise modeling in the nanometer regime table of contents

Pages: 376 - 381

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

Kanak Agarwal	University of Michigan, Ann Arbor, MI
Dennis Sylvester	University of Michigan, Ann Arbor, MI
David Blaauw	University of Michigan, Ann Arbor, MI

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 16, Citation Count: 6

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ABSTRACT

This paper presents a new library compatible approach to gate-level timing characterization in the presence of RLC interconnect loads. We describe a two-ramp model based on transmission line theory that accurately predicts both the 50% delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The approach does not rely on piecewise linear Thevenin voltage sources. It is compatible with existing library characterization methods and is computationally efficient. Results are compared with SPICE and demonstrate typical errors under 10% for both delay and slew rate.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 6

	Liang Zhang , Wentai Liu , Rizwan Bashirullah , John Wilson , Paul Franzon, Simplified delay design guidelines for on-chip global interconnects, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Lakshmi K. Vakati , Janet Wang, A new multi-ramp driver model with RLC interconnect load, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA
	Jeong-Taek Kong, CAD for nanometer silicon design challenges and success, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.11, p.1132-1147, November 2004
	Shahin Nazarian , Massoud Pedram , Tao Lin , Emre Tuncer, CGTA: current gain-based timing analysis for logic cells, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Shahin Nazarian , Massoud Pedram, Cell delay analysis based on rate-of-current change, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Amit Goel , Sarma Vrudhula, Current source based standard cell model for accurate signal integrity and timing analysis, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany