Parameter variations and impact on circuits and microarchitecture

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Parameter variations and impact on circuits and microarchitecture

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents

Anaheim, CA, USA

SESSION: Coping with variability: the end of deterministic design table of contents

Pages: 338 - 342

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

Shekhar Borkar	Intel Labs, Hillsboro, OR
Tanay Karnik	Intel Labs, Hillsboro, OR
Siva Narendra	Intel Labs, Hillsboro, OR
Jim Tschanz	Intel Labs, Hillsboro, OR
Ali Keshavarzi	Intel Labs, Hillsboro, OR
Vivek De	Intel Labs, Hillsboro, OR

Sponsor

ACM: Association for Computing Machinery

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ACM New York, NY, USA

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Downloads (6 Weeks): 42, Downloads (12 Months): 332, Citation Count: 159

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ABSTRACT

Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Bowman, K., et. al, "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration", IEEE Journal of Solid-State Circuits, Volume 37, Feb 2002, pp.183--190.
	2	Borkar, S., "Parameter Variations and Impact on Circuits & Microarchitecture", C2S2 MARCO review, March 2003.
	3	George Sery , Shekhar Borkar , Vivek De, Life is CMOS: why chase the life after?, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.513941]
	4	Tanay Karnik , Shekhar Borkar , Vivek De, Sub-90nm technologies: challenges and opportunities for CAD, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.203-206, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774602]
	5	Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514042]
	6	Tschanz, J., et al., "Design optimizations of a high performance microprocessor using combinations of dual-Vt allocation and transistor sizing", VLSI Circuits Symposium 2001, pp. 218--219.
	7	Tschanz, J., et al., "Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Micro-processors", ISSCC 2003, pp.102--103.
	8	Narendra, S., et al., "1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS", ISSCC 2002, pp. 270--271.
	9	A. Keshavarzi , S. Ma , S. Narendra , B. Bloechel , K. Mistry , T. Ghani , S. Borkar , V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, Proceedings of the 2001 international symposium on Low power electronics and design, p.207-212, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383135]
	10	Tschanz, J., et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage", ISSCC 2002, pp.422--423.
	11	Rahal-Arabi, T., et al., "Design and validation of the Pentium III and Pentium 4 processors power delivery", VLSI Symposium 2002, pp220--223.

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	Michele Favalli , Cecilia Metra, Testing resistive opens and bridging faults through pulse propagation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v.28 n.6, p.915-925, June 2009
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	Ashok Kumar Palaniswamy , Manoj Kumar Goparaju , Spyros Tragoudas, A fault tolerant threshold logic gate design, Proceedings of the 13th WSEAS international conference on Circuits, p.162-167, July 22-24, 2009, Rodos, Greece
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