Static leakage reduction through simultaneous threshold voltage and state assignment

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Static leakage reduction through simultaneous threshold voltage and state assignment

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents

Anaheim, CA, USA

SESSION: Managing leakage power table of contents

Pages: 191 - 194

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

Dongwoo Lee	University of Michigan, Ann Arbor, MI
David Blaauw	University of Michigan, Ann Arbor, MI

Sponsor

ACM: Association for Computing Machinery

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ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 29, Citation Count: 11

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ABSTRACT

We propose a new method that uses a combined approach of sleep-state assignment and threshold voltage (Vt) assignment in a dual-Vt process. While each of these methods has previously been used individually, their combined effect has not been leveraged to date. By combining Vt and sleep-state assignment, leakage current can be dramatically reduced since the circuit is in a known state in standby-mode and only transistors that are off need to be considered for high-Vt assignment. A significant improvement in the leakage/ performance trade-off is therefore achievable using such a combined method. We formulate the optimization problem for simultaneous state and Vt assignment under delay constraints and propose both an exact method for its optimal solution as well as a number of practical heuristics with reasonable run time. We compare our results with Vt and sleep state assignment only and demonstrate an average decrease in leakage current of 3.5X compared to previous approaches.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 11

	Dongwoo Lee , Wesley Kwong , David Blaauw , Dennis Sylvester, Analysis and minimization techniques for total leakage considering gate oxide leakage, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Puneet Gupta , Andrew B. Kahng , Puneet Sharma , Dennis Sylvester, Selective gate-length biasing for cost-effective runtime leakage control, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Anup Kumar Sultania , Dennis Sylvester , Sachin S. Sapatnekar, Tradeoffs between date oxide leakage and delay for dual T_ox circuits, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Dongwoo Lee , David Blaauw , Dennis Sylvester, Gate oxide leakage current analysis and reduction for VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.155-166, February 2004
	Dongwoo Lee , David Blaauw , Dennis Sylvester, Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Ashish Kumar Singh , Murari Mani , Ruchir Puri , Michael Orshansky, Gain-based technology mapping for minimum runtime leakage under input vector uncertainty, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Lara D. Oliver , Krishnendu Chakrabarty , Hisham Z. Massoud, An evaluation of the impact of gate oxide tunneling on dual-V_t-based leakage reduction techniques, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Saraju P. Mohanty , Ramakrishna Velagapudi , Elias Kougianos, Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits, Proceedings of the conference on Design, automation and test in Europe: Proceedings, March 06-10, 2006, Munich, Germany
	Dongwoo Lee , Harmander Deogun , David Blaauw , Dennis Sylvester, Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization, Proceedings of the conference on Design, automation and test in Europe, p.10494, February 16-20, 2004
	Ang-Chih Hsieh , Tzu-Teng Lin , Tsuang-Wei Chang , Tingting Hwang, A functionality-directed clustering technique for low-power MTCMOS design—computation of simultaneously discharging current, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-25, August 2007
	Ashish K. Singh , Michael Orshansky, Logic synthesis for reducing leakage power consumption under workload uncertainty, Proceedings of the 12th WSEAS international conference on Circuits, p.351-355, July 22-24, 2008, Heraklion, Greece