Implications of technology scaling on leakage reduction techniques

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Implications of technology scaling on leakage reduction techniques

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents

Anaheim, CA, USA

SESSION: Managing leakage power table of contents

Pages: 187 - 190

Year of Publication: 2003

ISBN:1-58113-688-9

Authors

Y.-F. Tsai	Penn State University
D. Duarte	LTD, Intel Corporation
N. Vijaykrishnan	Penn State University
M. J. Irwin	Penn State University

Sponsor

ACM: Association for Computing Machinery

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 24, Citation Count: 3

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

The impact of technology scaling on three run-time leakage reduction techniques (Input Vector Control, Body Bias Control and Power Supply Gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 0.25um, 0.18um, and 0.07um technologies. HSPICE simulation results and estimations with various functional units and memory structures are presented to support a comprehensive analysis.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Siva Narendra , Vivek De , Dimitri Antoniadis , Anantha Chandrakasan , Shekhar Borkar, Scaling of stack effect and its application for leakage reduction, Proceedings of the 2001 international symposium on Low power electronics and design, p.195-200, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383132]
	2	A. Keshavarzi , S. Ma , S. Narendra , B. Bloechel , K. Mistry , T. Ghani , S. Borkar , V. De, Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, Proceedings of the 2001 international symposium on Low power electronics and design, p.207-212, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383135]
	3	David Duarte , Yuh-Fang Tsai , Narayanan Vijaykrishnan , Mary Jane Irwin, Evaluating Run-Time Techniques for Leakage Power Reduction, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.31, January 07-11, 2002
	4	Ye, Y., Borkar, S., and De, V., "A New Technique for Standby Leakage Reduction in High-Performance Circuits," Sym. on VLSI Circuits, pp. 40--41, 1998
	5	Halter J., and Najm, F., "A Gate-level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits, IEEE CICC, pp. 475--478, 1997.
	6	David Enrique Duarte , Mary Jane Irwin, Clock network and phase-locked loop power estimation and experimentation, 2002

CITED BY 3

	Wei Wang , Yu Hu , Yin-He Han , Xiao-Wei Li , You-Sheng Zhang, Leakage current optimization techniques during test based on don't care bits assignment, Journal of Computer Science and Technology, v.22 n.5, p.673-680, September 2007
	Feng Gao , J. P. Hayes, Exact and heuristic approaches to input vector control for leakage power reduction, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.527-532, November 07-11, 2004
	Akhilesh Kumar , Mohab Anis, Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance, Proceedings of the 7th International Symposium on Quality Electronic Design, p.735-740, March 27-29, 2006