Distributed sleep transistor network for power reduction

ABSTRACT

Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.

REFERENCES

• 1: James Kao , Siva Narendra , Anantha Chandrakasan, Subthreshold leakage modeling and reduction techniques, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.141-148, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774593]
• 2: S.Mutah and et~al., "1-v power supply high-speed digital circuit technology with multithreshold-voltage cmos," IEEE Journal of Solid-State Circuits, August 1995.
• 3: James Kao , Siva Narendra , Anantha Chandrakasan, MTCMOS hierarchical sizing based on mutual exclusive discharge patterns, Proceedings of the 35th annual conference on Design automation, p.495-500, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277180]
• 4: Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
• 5: C. Long and L. He, "Distributed sleep transistor network for power reduction," tech. rep., UCLA EE Dept., http://eda.ee.ucla.edu/publications.html, 2003.
• 6: T. Sakurai and A. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, pp. 584--594, April 1990.
• 7: Yi-Min Jiang , Kwang-Ting Cheng , An-Chang Deng, Estimation of maximum power supply noise for deep sub-micron designs, Proceedings of the 1998 international symposium on Low power electronics and design, p.233-238, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280915]
• 8: Xiang-Dong Tan , C.-J. Richard Shi , Dragos Lungeanu , Jyh-Chwen Lee , Li-Pen Yuan, Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings, Proceedings of the 36th ACM/IEEE conference on Design automation, p.78-83, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309880]
• 9: Y. M. Jiang, K. T. Cheng, and A. Krstic, "Estimation of maximum power and instantaneous current using a genetic algorithm," in Proc. IEEE Custom Integrated Circuits Conf.., pp. 135--138, May 1997.
• 10: Angela Krstić , Kwang-Ting Cheng, Vector generation for maximum instantaneous current through supply lines for CMOS circuits, Proceedings of the 34th annual conference on Design automation, p.383-388, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266176]
• 11: E. M. Sentovich, K. J. Singh, L. Lavagno, and etc., "Sis: a system for sequential circuit synthesis," Memorandum NO. UCB/ERL M92/41, May 1992.
• 12: Weiping Liao , Joseph M. Basile , Lei He, Leakage power modeling and reduction with data retention, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.714-719, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774677]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles

General Terms:
Design