Analysis and minimization techniques for total leakage considering gate oxide leakage

ABSTRACT

In this paper we address the growing issue of gate oxide leakage current (Igate) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both Igate and subthreshold leakage (Isub). The interaction between Isub and Igate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of Igate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce Igate due to the dependence of gate leakage on stack node voltages.

REFERENCES

• 1: A. Ono, et al., "A 100nm node CMOS technology for practical SOC application requirement," Proc. IEDM, pp. 511--514, 2001.
• 2: 2001 International Technology Roadmap for Semiconductors.
• 3: B. Yu, et al., "Limits of gate oxide scaling in nano-transistors," Proc. Symp. VLSI Tech., pp. 90--91, 2000.
• 4: Y.-C. Yeo, et al., "Direct tunneling gate leakage current in transistors with ultra thin silicon nitride gate dielectric," IEEE Electron Device Letters, pp. 540--542, Nov. 2000.
• 5: C.-H. Choi, et al., "Impact of gate direct tunneling on circuit performance: a simulation study," IEEE Trans. Electron Devices, pp. 2823--2829, Dec. 2001.
• 6: S. Schwantes and W. Krautschneider, "Relevance of gate current for the functionality of deep submicron CMOS circuits," European Solid-State Device Research Conf., 2001.
• 7: Fatih Hamzaoglu , Mircea R. Stan, Circuit-level techniques to control gate leakage for sub-100nm CMOS, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566425]
• 8: http://www-device.eecs.berkeley.edu/~ptm
• 9: Dongwoo Lee , Wesley Kwong , David Blaauw , Dennis Sylvester, Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design, Proceedings of the 4th International Symposium on Quality Electronic Design, p.287, March 24-26, 2003
• 10: N. Yang, W. K. Henson, and J. J. Wortman, "A comparative study of gate direct tunneling and drain leakage currents in N-MOSFETs with sub-2nm gate oxides," IEEE Trans. Electron Devices, pp. 1636--1644, Aug. 2000.
• 11: Y. Taur, "CMOS design near the limit of scaling," IBM J. R&D, pp. 213--222, March/May 2002.
• 12: M.C. Johnson, et. al., "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Trans. CAD, pp. 714--725, June 1999.
• 13: J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," Proc. CICC, pp. 475--478, 1997.
• 14: Dongwoo Lee , David Blaauw, Static leakage reduction through simultaneous threshold voltage and state assignment, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775881]
• 15: S. Ercolani, M. Favalli, M. Damiani, P. Olivo, B. Ricco, "Estimate of signal probability in combinational logic networks," Proc. European Test Conference, 1989, pp. 132--138.
• 16: F. Brglez and H. Fujiwara, "A Neutral Netlist of 10 Combinatorial Benchmark Circuits", Proc. ISCAS, 1985, pp.695--698.
• 17: http://www.cbl.ncsu.edu

INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

General Terms:
Algorithms, Design, Performance, Reliability