ACM Home Page
Please provide us with feedback. Feedback
Large-scale SOP minimization using decomposition and functional properties
Full text PdfPdf (260 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents
Anaheim, CA, USA
SESSION: Cyclic and non-cyclic combinational circuit synthesis table of contents
Pages: 149 - 154  
Year of Publication: 2003
ISBN:1-58113-688-9
Authors
Alan Mishchenko  University of California, Berkeley, Berkeley, CA
Tsutomu Sasao  Kyushu Institute of Technology, Iizuka, Fukuoka, Japan
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 22,   Citation Count: 2
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/775832.775872
What is a DOI?

ABSTRACT

In some cases, minimum Sum-Of-Products (SOP) expressions of Boolean functions can be derived by detecting decomposition and observing the functional properties such as unateness, instead of applying the classical minimization algorithms. This paper presents a systematic study of such situations and develops a divide-and-conquer algorithm for SOP minimization, which can dramatically reduce the computational effort, without sacrificing the minimality of the solutions. The algorithm is used as a preprocessor to a general-purpose exact or heuristic minimizer, such as ESPRESSO. The experimental results show significant improvements in runtime. The exact solutions for some large MCNC benchmark functions are reported for the first time.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. L. Ashenhurst, "The decomposition of switching functions". Computation Lab, Harvard University, 1959, Vol. 29, pp. 74--116.
 
2
 
3
 
4
R. K. Brayton and C. McMullen, "The decomposition and factorization of Boolean expressions," Proc. ISCAS '82, pp. 29--54.
 
5
 
6
M.J. Ciesielski, S. Yang, and M.A. Perkowski, "Multiple-valued minimization based on graph coloring," Proc. ICCD '89, pp.262--265.
 
7
O. Coudert and J. C. Madre, "Towards a symbolic logic minimization algorithm", Proc. VLSI Design, January 1993.
 
8
9
 
10
J. Jacob and A. Mishchenko, "Unate decomposition of Boolean functions", Proc. IWLS '01, pp. 66--71.
11
 
12
Y. Matsunaga, "An exact and efficient algorithm for disjunctive decomposition", Proc. SASIMI '98, pp. 44--50.
13
 
14
S. Minato, "Fast generation of irredundant sum-of-products forms from binary decision diagrams. Proc. SASIMI'92, pp. 64--73.
 
15
A. Mishchenko, EXTRA Library of DD procedures. http://www.ee.pdx.edu/~alanmi/research/ extra.htm
 
16
R. L. Rudell and A. Sangiovanni-Vincentelli, "Multiple-valued minimization for PLA optimization", IEEE Trans. CAD, Vol. 6(5), pp. 727--750, Sep. 1987.
 
17
T. Sasao, "An algorithm to derive the complement of a binary function with multiple-valued inputs," IEEE Trans. Comp. Vol. C-34, No. 2, pp. 131--140, Feb. 1985.
18
 
19
 
20
T. Sasao, S. J. Hong, and R. K. Brayton, "Minimization of PLA's by decomposition", Unpublished technical report, 1984.
 
21
T. Sasao and M. Matsuura, "DECOMPOS: An integrated system for functional decomposition," Proc. IWLS '98, pp. 471--477.
 
22
E. Sentovich, et al, "SIS: A system for sequential circuit synthesis", Tech. Rep. UCB/ERI, M92/41, ERL, Dept. of EECS, Univ. of California, Berkeley, 1992.
 
23
F. Somenzi, BDD package "CUDD v. 2.3.0." http://vlsi.colorado.edu/~fabio/CUDD/cuddIntro.html
 
24


Collaborative Colleagues:
Alan Mishchenko: colleagues
Tsutomu Sasao: colleagues