A static pattern-independent technique for power grid voltage integrity verification

ABSTRACT

Design verification must include the power grid. Checking that the voltage on the power grid does not drop by more than some critical threshold is a very difficult problem, for at least two reasons: i) the obviously large size of the power grids for modern high-performance chips, and ii) the difficulty of setting up the right simulation conditions for the power grid that provide some measure of a realistic worst case voltage drop. The huge number of possible circuit operational modes or workloads makes it impossible to do exhaustive analysis. We propose a static technique for power grid verification, where static is in the sense of static timing analysis, meaning that it does not depend on, nor require, user-specified stimulus to drive a simulation. The verification is posed as an optimization problem under user-supplied current constraints. We propose that current constraints are the right kind of abstraction to use in order to develop a practical methodology for power grid verification. We present our verification approach, and report on the results of applying it to a number of test-case power grids.

REFERENCES

• 1: Abhijit Dharchoudhury , Rajendran Panda , David Blaauw , Ravi Vaidyanathan , Bogdan Tutuianu , David Bearden, Design and analysis of power distribution networks in PowerPC microprocessors, Proceedings of the 35th annual conference on Design automation, p.738-743, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277229]
• 2: Gregory Steele , David Overhauser , Steffen Rochel , Syed Zakir Hussain, Full-chip verification methods for DSM power distribution systems, Proceedings of the 35th annual conference on Design automation, p.744-749, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277231]
• 3: Min Zhao , Rajendran V. Panda , Sachin S. Sapatnekar , Tim Edwards , Rajat Chaudhry , David Blaauw, Hierarchical analysis of power distribution networks, Proceedings of the 37th conference on Design automation, p.150-155, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337355]
• 4: L. T. Pillage, R. A. Rohrer, and C. Visweswaraiah. Electronic Circuit and System Simulation Methods. McGraw-Hill, Inc., New York, NY, 1995.
• 5: G. H. Golub and C. F. Van Loan. Matrix Computations. The Johns Hopkins University Press, 1996.
• 6: A. Berman and R. J. Plemmons. Nonnegative Matrices in the Mathematical Science. Academic Press, New York, 1996.
• 7: H. Kriplani, F. N. Najm, and I. Hajj. Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: algorithms, signal correlations, and their resolution. IEEE Transactions on Computer-Aided Design, 14(8):998--1012, August 1995.
• 8: Jorge Rubenstein, Paul Penfield, and Mark A. Horowitz. Signal delay in RC tree networks. IEEE Trans. on Computer-Aided Design, 2(3):202--211, July 1983.
• 9: D. G. Luenberger. Linear and Nonlinear Programming. Addison-Wesley, Reading, MA, 2nd edition, 1984.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids

General Terms:
Algorithms, Design, Verification

Keywords:
power grid, stat, voltage drop