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Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 40th annual Design Automation Conference table of contents
Anaheim, CA, USA
SESSION: Embedded hardware design case studies table of contents
Pages: 60 - 65  
Year of Publication: 2003
ISBN:1-58113-688-9
Authors
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 10,   Downloads (12 Months): 30,   Citation Count: 2
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ABSTRACT

This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents the concept of HW/SW acceleration transparency, a systematic method to accelerate Java functions in both software and hardware. An example of acceleration transparency for a Rijndael encryption function is presented. The embedded prototype hardware platform is also described. Acceleration transparency yields software and hardware performance gains of 333X.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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H. Kuo, P. Schaumont, and I. Verbauwhede, "A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 um CMOS technology," Proc. 2002 Custom Integrated Circuits Conference, pp. 147--50, May 2002.
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J. Gaisler, The LEON2 IEEE-1754 (SPARC V8) Processor, http://www.gaisler.com.
 
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Collaborative Colleagues:
David Hwang: colleagues
Bo-Cheng Lai: colleagues
Patrick Schaumont: colleagues
Kazuo Sakiyama: colleagues
Yi Fan: colleagues
Shenglin Yang: colleagues
Alireza Hodjat: colleagues
Ingrid Verbauwhede: colleagues