Optimizing pipelines for power and performance

ABSTRACT

During the concept phase and definition of next generation high-end processors, power and performance will need to be weighted appropriately to deliver competitive cost/performance. It is not enough to adopt a CPl-centric view alone in early-stage definition studies. One of the fundamental issues confronting the architect at this stage is the choice of pipeline depth and target frequency. In this paper we present an optimization methodology that starts with an analytical power-performance model to derive optimal pipeline depth for a superscalar processor. The results are validated and further refined using detailed simulation based analysis. As part of the power-modeling methodology, we have developed equations that model the variation of energy as a function of pipeline depth. Our results using a set of SPEC2000 applications show that when both power and performance are considered for optimization, the optimal clock period is around 18 F04. We also provide a detailed sensitivity analysis of the optimal pipeline depth against key assumptions of these energy models.

REFERENCES

• 1: David M. Brooks , Pradip Bose , Stanley E. Schuster , Hans Jacobson , Prabhakar N. Kudva , Alper Buyuktosunoglu , John-David Wellman , Victor Zyuban , Manish Gupta , Peter W. Cook, Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors, IEEE Micro, v.20 n.6, p.26-44, November 2000 [doi>10.1109/40.888701]
• 2: David Brooks , Vivek Tiwari , Margaret Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, Proceedings of the 27th annual international symposium on Computer architecture, p.83-94, June 2000, Vancouver, British Columbia, Canada
• 3: David Brooks , Margaret Martonosi , John-David Wellman , Pradip Bose, Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor, Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers, p.126-136, November 12, 2000
• 4: Mary D. Brown , Jared Stark , Yale N. Patt, Select-free instruction scheduling logic, Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, December 01-05, 2001, Austin, Texas
• 5: Pradeep K. Dubey , Michael J. Flynn, Optimal pipelining, Journal of Parallel and Distributed Computing, v.8 n.1, p.10-19, Jan. 1990 [doi>10.1016/0743-7315(90)90064-V]
• 6: P. G. Emma , E. S. Davidson, Characterization of branch and data dependencies on programs for evaluating pipeline performance, IEEE Transactions on Computers, v.36 n.7, p.859-875, July 1987 [doi>10.1109/TC.1987.1676981]
• 7: Michael J. Flynn , Patrick Hung , Kevin W. Rudd, Deep-Submicron Microprocessor Design Issues, IEEE Micro, v.19 n.4, p.11-22, July 1999 [doi>10.1109/40.782563]
• 8: R. Gonzalez and M. Horowitz. Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 31(9): 1277--84, Sept. 1996.
• 9: A. Hartstein , Thomas R. Puzak, The optimum pipeline depth for a microprocessor, Proceedings of the 29th annual international symposium on Computer architecture, p.7, May 25-29, 2002, Anchorage, Alaska
• 10: Seongmoo Heo , Ronny Krashinsky , Krste Asanovic, Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy, Proceedings of the 2001 Conference on Advanced Research in VLSI, p.59, March 14-16, 2001
• 11: M. S. Hrishikesh , Doug Burger , Norman P. Jouppi , Stephen W. Keckler , Keith I. Farkas , Premkishore Shivakumar, The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays, Proceedings of the 29th annual international symposium on Computer architecture, p.14, May 25-29, 2002, Anchorage, Alaska
• 12: Vijay S. Iyengar , Louise H. Trevillyan , Pradip Bose, Representative Traces for Processor Models with Infinite Cache, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.62, February 03-07, 1996
• 13: R. M. Jessani , C. H. Olson, The floating-point unit of the PowerPC 603e microprocessor, IBM Journal of Research and Development, v.40 n.5, p.559-566, Sept. 1996
• 14: Peter M. Kogge, The Architecture of Symbolic Computers, McGraw-Hill, Inc., New York, NY, 1990
• 15: S. R. Kunkel , J. E. Smith, Optimal pipelining in supercomputers, Proceedings of the 13th annual international symposium on Computer architecture, p.404-411, June 02-05, 1986, Tokyo, Japan
• 16: M. Moudgill, P. Bose, and J. Moreno. Validation of Turandot, a fast processor model for microarchitecture exploration. In Proceedings of the IEEE International Performance, Computing, and Communications Conference (IPCCC), pages 451--457, Feb. 1999.
• 17: Mayan Moudgill , John-David Wellman , Jaime H. Moreno, Environment for PowerPC Microarchitecture Exploration, IEEE Micro, v.19 n.3, p.15-25, May 1999 [doi>10.1109/40.768496]
• 18: J. S. Neely, H. H. Chen, S. G. Walker, J. Venuto, and T. Bucelot. CPAM: A common power analysis methodology for high-performance VLSI design. In Proc. of the 9th Topical Meeting on the Electrical Performance of Electronic Packaging, pages 303--306, 2000.
• 19: Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
• 20: P. Song and G. D. Micheli. Circuit and architecture tradeoffs for high-speed multiplication. IEEE Journal of Solid-State Circuits, 26(9): 1184--1198, Sept. 1991.
• 21: Eric Sprangle , Doug Carmean, Increasing processor performance by implementing deeper pipelines, Proceedings of the 29th annual international symposium on Computer architecture, p.25, May 25-29, 2002, Anchorage, Alaska
• 22: Jared Stark , Mary D. Brown , Yale N. Patt, On pipelining dynamic instruction scheduling logic, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.57-66, December 2000, Monterey, California, United States [doi>10.1145/360128.360136]
• 23: N. Vijaykrishnan , M. Kandemir , M. J. Irwin , H. S. Kim , W. Ye, Energy-driven integrated hardware-software optimizations using SimplePower, Proceedings of the 27th annual international symposium on Computer architecture, p.95-106, June 2000, Vancouver, British Columbia, Canada
• 24: Victor V. Zyuban , Peter M. Kogge, Inherently lower-power high-performance superscalar architectures, 2000
• 25: V. Zyuban , D. Meltzer, Clocking strategies and scannable latches for low power appliacations, Proceedings of the 2001 international symposium on Low power electronics and design, p.346-351, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383181]
• 26: Victor Zyuban , Philip Strenski, Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566451]

INDEX TERMS

Primary Classification:
  D. Software
  D.3 PROGRAMMING LANGUAGES
      D.3.4 Processors
          Subjects: Optimization

Additional Classification:
  D. Software
  D.4 OPERATING SYSTEMS
      D.4.8 Performance
          Subjects: Simulation

General Terms:
Performance