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 ABSTRACT
The Dynamic Execution Layer Interface (DELl) offers the following unique capability: it provides fine-grain control over the execution of programs, by allowing its clients to observe and optionally manipulate every single instruction---at run time---just before it runs. DELl accomplishes this by opening up an interface to the layer between the execution of software and hardware. To avoid the slowdown, DELl caches a private copy of the executed code and always runs out of its own private cache.In addition to giving powerful control to clients, DELl opens up caching and linking to ordinary emulators and just-in-time compilers, which then get the reuse benefits of the same mechanism. For example, emulators themselves can also use other clients, to mix emulation with already existing services, native code, and other emulators.This paper describes the basic aspects of DELl, including the underlying caching and linking mechanism, the Hardware Abstraction Mechanism (HAM), the Binary-Level Translation (BLT) infrastructure, and the Application Programming interface (API) exposed to the clients. We also cover some of the services that clients could offer through the DELl, such as ISA emulation, software patching, and sandboxing. Finally, we consider a case study of emulation in detail: the emulation of a PocketPC system on the Lx/ST210 embedded VLIW processor. In this case, DELl enables us to achieve near-native performance, and to mix-and-match native and emulated code.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
Vasanth Bala , Evelyn Duesterwald , Sanjeev Banerjia, Dynamo: a transparent dynamic optimization system, Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, p.1-12, June 18-21, 2000, Vancouver, British Columbia, Canada
|
| |
2
|
|
| |
3
|
T. Baji, N. Kawashimo, I. Kawasaki, and K. Noguchi. SuperH and SuperH-DSP Microprocessors for the Mobile Computing Age. Hitachi Review, Vol. 46 No. 1. Feb 1997.
|
| |
4
|
|
| |
5
|
F. Chang, A. Itzkovitz, and V. Karamcheti. User-level Resource-Constrained Sandboxing. 4th USENIX Windows Systems Symposium, August 2000.
|
| |
6
|
W. Chen, S. Lerner, R. Chaiken, and D. Gillies. Mojo: A dynamic optimization system. In Proc. 3rd Workshop on Feedback-Directed and Dynamic Optimization, Dec. 2000.
|
| |
7
|
R.F. Cmelik and D. Keppel. Shade: a fast instruction set simulator for execution profiling. TR UWCSE-93-06-06, Dept. Comp. Science and Eng., Univ. Washington. 1993
|
| |
8
|
D. Deaver, R. Gorton, and N. Rubin. Wiggins/Redstone: An on-line program specializer. In Hot Chips 11, Palo Alto, CA, Aug. 1999.
|
| |
9
|
D. Ditzel. Transmeta's Crusoe: Cool chips for mobile computing. In Hot Chips 12: Stanford University. Aug. 2000.
|
| |
10
|
"DynamoRlO" <u>http://www.cag.lcs.mit.edu/dynamorio/</u>
|
| |
11
|
|
| |
12
|
K. Ebcioglu, E.R. Altman, E. Hokenek. A JAVA ILP Machine Based on Fast Dynamic Compilation. IEEE MASCOTS International Workshop on Security and Efficiency Aspects of Java. Eilat, Israel, January 9--10, 1997.
|
| |
13
|
Paolo Faraboschi , Geoffrey Brown , Joseph A. Fisher , Giuseppe Desoli , Fred Homewood, Lx: a technology platform for customizable VLIW embedded processing, Proceedings of the 27th annual international symposium on Computer architecture, p.203-213, June 2000, Vancouver, British Columbia, Canada
|
| |
14
|
P. Faraboschi, F. Homewood, ST200: A VLIW Architecture for Media-Oriented Applications, Microprocessor Forum 2000, October 9--13 2000, San Jose, CA
|
| |
15
|
J. Fisher. Trace scheduling: a technique for global microcode compaction. IEEE Trans. on Computers, vol. 30, no. 9, 1981, pp. 478--490.
|
| |
16
|
|
| |
17
|
|
| |
18
|
M.R. Guthaus, J.S. Ringenberg, D. Ernst, T.M. Austin, T. Mudge and R.B. Brown. MiBench: A Free, Commercially Representative Embedded Benchmark Suite. 4th Workshop on Workload Characterization, Dec. 2001, Austin, TX
|
| |
19
|
H. Maejima, M. Kainaga, K. Uchiyama. Design and architecture for low-power/high-speed RISC microprocessor: SuperH. IEICE Trans. on Electronics. Vol. E80-C, No. 12. Dec. 1997.
|
| |
20
|
A. Klaiber. The Technology Behind Crusoe Processors. © 2000 Transmeta Corp. Available as: <u>www.transmeta.com/pdf/white papers/paper aklaiber_19jan00.pdf</u>
|
| |
21
|
|
| |
22
|
Matthew C. Merten , Andrew R. Trick , Christopher N. George , John C. Gyllenhaal , Wen-mei W. Hwu, A hardware-driven profiling scheme for identifying program hot spots to support runtime optimization, Proceedings of the 26th annual international symposium on Computer architecture, p.136-147, May 01-04, 1999, Atlanta, Georgia, United States
|
| |
23
|
Microsoft Corp. .NET specifications. Available at <u>http :www.microsoft.com/net/</u>
|
| |
24
|
A. Robinson. Why Dynamic Translation? © 2001 Transitive Technologies. Available as: <u>http:www.transitives.com/downloads/Why Dynamic Translation1.pdf</u>
|
| |
25
|
|
| |
26
|
K. Scott, J. Davidson. Strata: a software dynamic translation infrastructure. Proc. Workshop on Binary Translation, 2000.
|
| |
27
|
A. Srivastava H. Edwards, H. Vo. Vulcan: Binary translation in a distributed environment. Technical Report MSRTR-2001-50, Microsoft Research, 2001.
|
| |
28
|
|
| |
29
|
|
| |
30
|
|
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James C. Dehnert , Brian K. Grant , John P. Banning , Richard Johnson , Thomas Kistler , Alexander Klaiber , Jim Mattson, The Transmeta Code Morphing™ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, March 23-26, 2003, San Francisco, California
|
|
|
|
|
|
|
|
|
Naveen Kumar , Bruce R. Childers , Mary Lou Soffa, Tdb: a source-level debugger for dynamically translated programs, Proceedings of the sixth international symposium on Automated analysis-driven debugging, p.123-132, September 19-21, 2005, Monterey, California, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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Sanjay Bhansali , Wen-Ke Chen , Stuart de Jong , Andrew Edwards , Ron Murray , Milenko Drinić , Darek Mihočka , Joe Chau, Framework for instruction-level tracing and analysis of program executions, Proceedings of the second international conference on Virtual execution environments, June 14-16, 2006, Ottawa, Ontario, Canada
|
|
|
|
|
|
|
|
|
Oliverio J. Santana , Ayose Falcón , Alex Ramirez , Mateo Valero, Branch predictor guided instruction decoding, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
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|
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Jose Baiocchi , Bruce R. Childers , Jack W. Davidson , Jason D. Hiser , Jonathan Misurda, Fragment cache management for dynamic binary translators in embedded systems with scratchpad, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
|
|
|
José A. Baiocchi , Bruce R. Childers , Jack W. Davidson , Jason D. Hiser, Reducing pressure in bounded DBT code caches, Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems, October 19-24, 2008, Atlanta, GA, USA
|
|
|
Tobias Werth , Tobias Flossmann , Michael Klemm , Dominic Schell , Ulrich Weigand , Michael Philippsen, Dynamic code footprint optimization for the IBM Cell Broadband Engine, Proceedings of the 2009 ICSE Workshop on Multicore Software Engineering, p.64-72, May 18-18, 2009
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