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Communication speed selection for embedded systems with networked voltage-scalable processors
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Source International Conference on Hardware Software Codesign archive
Proceedings of the tenth international symposium on Hardware/software codesign table of contents
Estes Park, Colorado
SESSION: Energy efficiency in system design table of contents
Pages: 169 - 174  
Year of Publication: 2002
ISBN:1-58113-542-4
Authors
Jinfeng Liu  University of California, Irvine, CA
Pai H. Chou  University of California, Irvine, CA
Nader Bagherzadeh  University of California, Irvine, CA
Sponsors
IEEE-CS\DATC : IEEE Computer Society
IFIP WG 10.5 : IFIP WG 10.5
SIGSOFT: ACM Special Interest Group on Software Engineering
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 14,   Citation Count: 11
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ABSTRACT

High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power efficiency. Many such interfaces also support multiple data rates, and this ability is opening a new dimension in the power/performance trade-offs between communication and computation on voltage scalable embedded processors. To minimize energy consumption in these networked architectures, designers must not only perform functional partitioning but also carefully balance the speeds between communication and computation, which compete for time and energy. Minimizing communication power without considering computation may actually lead to higher energy consumption at the system level due to elongated on-time as well as lost opportunities for dynamic voltage scaling on the processors. We propose a speed selection methodology for globally optimizing the energy consumption in embedded networked architectures. We formulate a multi-dimensional optimization problem by modeling communication dependencies between processors and their timing budgets. This enables engineers to systematically solve the problem of optimal speed selection for global energy reduction. We demonstrate the effectiveness of our speed selection approach with an image processing application mapped onto a multi-processor architecture with a multi-speed Ethernet.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
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INTEL XScale microarchitecture. http://developer.intel.com/design/intelxscale/.
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P. V. Knudsen and J. Madsen. Integrating communication protocol selection with hardware/software codesign. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 18(8):1077--1095, August 1999.
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R. Sims. Signal to clutter measurement and ATR performance. Proc. of the SPIE -- The International Society for Optical Engineering, 3371(1):13--17, April 1998.
 
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CITED BY  11

Collaborative Colleagues:
Jinfeng Liu: colleagues
Pai H. Chou: colleagues
Nader Bagherzadeh: colleagues