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Compiler-directed customization of ASIP cores
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Source International Conference on Hardware Software Codesign archive
Proceedings of the tenth international symposium on Hardware/software codesign table of contents
Estes Park, Colorado
SESSION: Co-design architecture and synthesis table of contents
Pages: 97 - 102  
Year of Publication: 2002
ISBN:1-58113-542-4
Authors
T. Vinod Kumar Gupta  University of Maryland, College Park, MD
Roberto E. Ko  Cornell University, Ithaca, NY
Rajeev Barua  University of Maryland, College Park, MD
Sponsors
IEEE-CS\DATC : IEEE Computer Society
IFIP WG 10.5 : IFIP WG 10.5
SIGSOFT: ACM Special Interest Group on Software Engineering
: IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 7,   Downloads (12 Months): 19,   Citation Count: 6
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ABSTRACT

This paper presents an automatic method to customize embedded application-specific instruction processors (ASIPs) based on compiler analysis. ASIPs, also known as embedded soft cores, allow certain hardware parameters in the processor to be customized for a specific application domain. They offer low design cost as they use pre-designed and verified components. Our design goal is choosing parameter values for fastest runtime within a given silicon area budget for a particular application set. Present-day technologies for choosing parameter values rely on exhaustive simulation of the application set on all possible combinations of parameter values -- a time-consuming and non-scalable procedure. We propose a compiler-based method that automatically derives the optimal values of parameters without simulating any configuration. Further, we expand the space of parameters that can be changed from the limited set today, and evaluate the importance of each. Results show that for our benchmarks, the runtimes for different configurations are predicted with an average error of 2.5%. In the two area constrained customization problem we evaluate, our method is able to recommend the same configuration that is recommended by brute force exhaustive simulation.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Technical Summary of the ARC Core. ARC Cores Ltd, 2000. At http://www.arccores.com.
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J. A. Fisher, P. Faraboschi, and G. Desoli. Custom-Fit Processors. Technical report, Hewlett Packard Laboratory, 1501, Page Mill Road, Palo Alto, CA 94304, 1997.
 
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M. Flynn. EE382 Processor Design: Silicon Area and Cost Models. Course handout, EE382, Stanford Univ., 1999.
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G. Goossens, J. Praet, D. Lanneer, W. Geurts, A. Kilfi, C. Liem, and P. Paulin. Embedded Software in Real-Time Signal Processing Systems: Design Technologies. Invited paper, Proceedings of the IEEE, 85(3), March 1997.
 
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C. Lee and M. Stoodley. UTDSP BenchMark Suite. 1992. http://www.eecg.toronto.edu/~corinna/DSP/infrastructure/UTDSP.html.
 
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J. Turley. Tensilica CPU Bends to Designers' Will. Microprocessor Report, 13(3): 12, March 8 1999.

CITED BY  6

Collaborative Colleagues:
T. Vinod Kumar Gupta: colleagues
Roberto E. Ko: colleagues
Rajeev Barua: colleagues