| Compiler-directed customization of ASIP cores |
| Full text |
Pdf
(629 KB)
|
| Source
|
International Conference on Hardware Software Codesign
archive
Proceedings of the tenth international symposium on Hardware/software codesign
table of contents
Estes Park, Colorado
SESSION: Co-design architecture and synthesis
table of contents
Pages: 97 - 102
Year of Publication: 2002
ISBN:1-58113-542-4
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 7, Downloads (12 Months): 19, Citation Count: 6
|
|
|
ABSTRACT
This paper presents an automatic method to customize embedded application-specific instruction processors (ASIPs) based on compiler analysis. ASIPs, also known as embedded soft cores, allow certain hardware parameters in the processor to be customized for a specific application domain. They offer low design cost as they use pre-designed and verified components. Our design goal is choosing parameter values for fastest runtime within a given silicon area budget for a particular application set. Present-day technologies for choosing parameter values rely on exhaustive simulation of the application set on all possible combinations of parameter values -- a time-consuming and non-scalable procedure. We propose a compiler-based method that automatically derives the optimal values of parameters without simulating any configuration. Further, we expand the space of parameters that can be changed from the limited set today, and evaluate the importance of each. Results show that for our benchmarks, the runtimes for different configurations are predicted with an average error of 2.5%. In the two area constrained customization problem we evaluate, our method is able to recommend the same configuration that is recommended by brute force exhaustive simulation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Technical Summary of the ARC Core. ARC Cores Ltd, 2000. At http://www.arccores.com.
|
 |
2
|
Paolo Faraboschi , Geoffrey Brown , Joseph A. Fisher , Giuseppe Desoli , Fred Homewood, Lx: a technology platform for customizable VLIW embedded processing, Proceedings of the 27th annual international symposium on Computer architecture, p.203-213, June 2000, Vancouver, British Columbia, Canada
|
| |
3
|
J. A. Fisher, P. Faraboschi, and G. Desoli. Custom-Fit Processors. Technical report, Hewlett Packard Laboratory, 1501, Page Mill Road, Palo Alto, CA 94304, 1997.
|
| |
4
|
M. Flynn. EE382 Processor Design: Silicon Area and Cost Models. Course handout, EE382, Stanford Univ., 1999.
|
 |
5
|
Naji Ghazal , Richard Newton , Jan Rabaey, Predicting performance potential of modern DSPs, Proceedings of the 37th conference on Design automation, p.332-335, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337431]
|
| |
6
|
|
| |
7
|
G. Goossens, J. Praet, D. Lanneer, W. Geurts, A. Kilfi, C. Liem, and P. Paulin. Embedded Software in Real-Time Signal Processing Systems: Design Technologies. Invited paper, Proceedings of the IEEE, 85(3), March 1997.
|
| |
8
|
|
 |
9
|
|
| |
10
|
|
| |
11
|
C. Lee and M. Stoodley. UTDSP BenchMark Suite. 1992. http://www.eecg.toronto.edu/~corinna/DSP/infrastructure/UTDSP.html.
|
| |
12
|
|
 |
13
|
Barry Shackleford , Mitsuhiro Yasuda , Etsuko Okushi , Hisao Koizumi , Hiroyuki Tomiyama , Hiroto Yasuura, Memory-CPU size optimization for embedded system designs, Proceedings of the 34th annual conference on Design automation, p.246-251, June 09-13, 1997, Anaheim, California, United States
[doi> 10.1145/266021.266083]
|
| |
14
|
J. Turley. Tensilica CPU Bends to Designers' Will. Microprocessor Report, 13(3): 12, March 8 1999.
|
CITED BY 6
|
|
|
|
|
Shobana Padmanabhan , Phillip Jones , David V. Schuehler , Scott J. Friedman , Praveen Krishnamurthy , Huakai Zhang , Roger Chamberlain , Ron K. Cytron , Jason Fritts , John W. Lockwood, Extracting and improving microarchitecture performance on reconfigurable architectures, International Journal of Parallel Programming, v.33 n.2, p.115-136, June 2005
|
|
|
|
|
|
|
|
|
|
|
|
|
|