Frame-based dynamic voltage and frequency scaling for a MPEG decoder

ABSTRACT

This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption while maintaining a quality of servic(QoS) constraint. The computational workload for an incoming frame is predicted using a frame-based history so that the processor voltage and frequency can be scaled to provide the exact amount of computing power needed to decode the frame. More precisely, the required decoding time for each frame is separated into two parts: a frame-dependent (FD) part and a frame-independent (FI) part. The FD part varies greatly according to the type of the incoming frame whereas the FI part remains constant regardless of the frame type. In the DVFS scheme presented in this paper the FI part is used to compensate for the prediction error that may occur during the FD part such that a significant amount of energy can be saved while meeting the frame rate requirement. The proposed DVFS algorithm has been implemented on a StrongArm-1110 based evaluation board. Measurement results demonstrate a higher than 50% CPU energy saving as a result of DVFS.

REFERENCES

• 1: M. Horowitz, T. Indermaur, and R. Gonzalez, "Low-power digital design," IEEE Symp. on Low Power Electronics, 1994, pp. 8--11.
• 2: M. Weiser, B. Welch, A. Demers, and S. Shenker, "Scheduling for reduced CPU energy," in Proc. 1st Symp on Operating Systems Design Implementation, 1994, pp. 13--23.
• 3: Kinshuk Govil , Edwin Chan , Hal Wasserman, Comparing algorithm for dynamic speed-setting of a low-power CPU, Proceedings of the 1st annual international conference on Mobile computing and networking, p.13-25, November 13-15, 1995, Berkeley, California, United States [doi>10.1145/215530.215546]
• 4: A. Chandrakasan , V. Gutnik , T. Xanthopoulos, Data driven signal processing: an approach for energy efficient computing, Proceedings of the 1996 international symposium on Low power electronics and design, p.347-352, August 12-14, 1996, Monterey, California, United States
• 5: Dongkun Shin , Jihong Kim , Seongsoo Lee, Low-energy intra-task voltage scheduling using static timing analysis, Proceedings of the 38th conference on Design automation, p.438-443, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.378551]
• 6: Seongsoo Lee , Takayasu Sakurai, Run-time power control scheme using software feedback loop for low-power real-time application, Proceedings of the 2000 conference on Asia South Pacific design automation, p.381-386, January 2000, Yokohama, Japan [doi>10.1145/368434.368693]
• 7: Joan L. Mitchell , William B. Pennebaker , Chad E. Fogg , Didier J. Legall, MPEG Video Compression Standard, Chapman & Hall, Ltd., London, UK, 1996
• 8: http://developer.intel.com/design/strong.
• 9: Ketan Patel , Brian C. Smith , Lawrence A. Rowe, Performance of a software MPEG video decoder, Proceedings of the first ACM international conference on Multimedia, p.75-82, August 02-06, 1993, Anaheim, California, United States [doi>10.1145/166266.166274]
• 10: Andy C. Bavier , A. Brady Montz , Larry L. Peterson, Predicting MPEG execution times, Proceedings of the 1998 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, p.131-140, June 22-26, 1998, Madison, Wisconsin, United States
• 11: J. Pouwelse, K. Langendoen, R. Lagendijk, and H. Sips,"Power-aware video decoding," presented at the 22nd Picture Coding Symposium, Seoul, Korea, 2001.
• 12: T. Burd, T. Pering, A. Stratakos, and R. Brodersen, "A dynamic voltage scaled microprocessor system," IEEE Journal of Solid-State Circuit, vol. 35, no. 11, Nov. 2000, pp. 1571--1580.
• 13: http://bmrc.berkeley.edu/frame/research/mpeg.
• 14: Trevor Pering , Tom Burd , Robert Brodersen, The simulation and evaluation of dynamic voltage scaling algorithms, Proceedings of the 1998 international symposium on Low power electronics and design, p.76-81, August 10-12, 1998, Monterey, California, United States [doi>10.1145/280756.280790]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.2 COMPUTER-COMMUNICATION NETWORKS
      C.2.1 Network Architecture and Design
          Subjects: Wireless communication

Additional Classification:
  C. Computer Systems Organization
  C.5 COMPUTER SYSTEM IMPLEMENTATION
      C.5.4 VLSI Systems

  H. Information Systems
  H.4 INFORMATION SYSTEMS APPLICATIONS
      H.4.3 Communications Applications

  I. Computing Methodologies
  I.1 SYMBOLIC AND ALGEBRAIC MANIPULATION
      I.1.2 Algorithms
          Subjects: Analysis of algorithms

  J. Computer Applications
  J.7 COMPUTERS IN OTHER SYSTEMS
      Subjects: Real time

General Terms:
Algorithms, Design, Experimentation, Theory