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Efficient instruction encoding for automatic instruction set design of configurable ASIPs
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 649 - 654  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Jong-eun Lee  Univ. of California, Irvine, Irvine, CA
Kiyoung Choi  Seoul National University, Seoul, South KOREA
Nikil Dutt  Univ. of California, Irvine Irvine, CA
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 28,   Citation Count: 16
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ABSTRACT

Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instructions is to convert application-specific operation patterns into new complex instructions. However, processors with a fixed instruction bitwidth cannot accommodate all the potentially interesting operation patterns, due to the limited code space afforded by the fixed instruction bitwidth. We present a novel instruction set synthesis technique that employs an efficient instruction encoding method to achieve maximal performance improvement. We build a library of complex instructions with various encoding alternatives and select the best set of complex instructions while satisfying the instruction bitwidth constraint. We formulate the problem using integer linear programming and also present an effective heuristic algorithm. Experimental results using our technique generate instruction sets that show improvements of up to 38% over the native instruction set for several realistic benchmark applications running on a typical embedded RISC processor.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Tensilica Inc., http://www.tensilica.com/.
 
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ARC Cores Inc., http://www.arc.com/.
 
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A. Cataldo, "Compiler that converts C-code to processor gates advances," EE Times, Oct. 23, 2001, http://www.eet.com/story/OEG20011023S0028.
 
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Y. Zhao et al., "Matching architecture to application via configurable processors," In Proc. ICCD 2001.
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A. Alomary et al., "PEAS-I: A hardware/software co-design system for ASIPs," In Proc. EURO-DAC 1993.
 
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I.-J. Huang and A. Despain, "Synthesis of application specific instruction sets," IEEE Trans. on CAD, 1995.
 
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D. Gajski, High-Level Synthesis, Kluwer Academic Publishers, 1992.
 
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SH-3/SH-3E/SH3-DSP Programming Manual, Hitachi, Ltd., 2000, available at http://www.hitachi-eu.com/hel/ecg/products/micro/pdf/sh7700p.pdf.
 
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J. Lee et al., "Automatic instruction set design through efficient instruction encoding for application-specific processors," Tech. Report, #02--23, CECS, UC Irvine.
 
14
EXPRESS Retargetable Compiler, Univ. of California, Irvine, Project website http://www.cecs.uci.edu/~aces/.
 
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CITED BY  16

Collaborative Colleagues:
Jong-eun Lee: colleagues
Kiyoung Choi: colleagues
Nikil Dutt: colleagues