| Efficient instruction encoding for automatic instruction set design of configurable ASIPs |
| Full text |
Pdf
(357 KB)
|
| Source
|
International Conference on Computer Aided Design
archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California
Pages: 649 - 654
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 28, Citation Count: 16
|
|
|
ABSTRACT
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instructions is to convert application-specific operation patterns into new complex instructions. However, processors with a fixed instruction bitwidth cannot accommodate all the potentially interesting operation patterns, due to the limited code space afforded by the fixed instruction bitwidth. We present a novel instruction set synthesis technique that employs an efficient instruction encoding method to achieve maximal performance improvement. We build a library of complex instructions with various encoding alternatives and select the best set of complex instructions while satisfying the instruction bitwidth constraint. We formulate the problem using integer linear programming and also present an effective heuristic algorithm. Experimental results using our technique generate instruction sets that show improvements of up to 38% over the native instruction set for several realistic benchmark applications running on a typical embedded RISC processor.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
| |
2
|
Tensilica Inc., http://www.tensilica.com/.
|
| |
3
|
ARC Cores Inc., http://www.arc.com/.
|
| |
4
|
A. Cataldo, "Compiler that converts C-code to processor gates advances," EE Times, Oct. 23, 2001, http://www.eet.com/story/OEG20011023S0028.
|
| |
5
|
Y. Zhao et al., "Matching architecture to application via configurable processors," In Proc. ICCD 2001.
|
 |
6
|
|
| |
7
|
A. Alomary et al., "PEAS-I: A hardware/software co-design system for ASIPs," In Proc. EURO-DAC 1993.
|
| |
8
|
Johan Van Praet , Gert Goossens , Dirk Lanneer , Hugo De Man, Instruction set definition and instruction selection for ASIPs, Proceedings of the 7th international symposium on High-level synthesis, p.11-16, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
|
| |
9
|
Hoon Choi , Jong-Sun Kim , Chi-Won Yoon , In-Cheol Park , Seung Ho Hwang , Chong-Min Kyung, Synthesis of Application Specific Instructions for Embedded DSP Software, IEEE Transactions on Computers, v.48 n.6, p.603-614, June 1999
[doi> 10.1109/12.773797]
|
| |
10
|
I.-J. Huang and A. Despain, "Synthesis of application specific instruction sets," IEEE Trans. on CAD, 1995.
|
| |
11
|
D. Gajski, High-Level Synthesis, Kluwer Academic Publishers, 1992.
|
| |
12
|
SH-3/SH-3E/SH3-DSP Programming Manual, Hitachi, Ltd., 2000, available at http://www.hitachi-eu.com/hel/ecg/products/micro/pdf/sh7700p.pdf.
|
| |
13
|
J. Lee et al., "Automatic instruction set design through efficient instruction encoding for application-specific processors," Tech. Report, #02--23, CECS, UC Irvine.
|
| |
14
|
EXPRESS Retargetable Compiler, Univ. of California, Irvine, Project website http://www.cecs.uci.edu/~aces/.
|
| |
15
|
lp_solve, Version 3.2, available at ftp://ftp.ics.ele.tue.nl/pub/lp_solve/.
|
CITED BY 16
|
|
Achim Nohl , Volker Greive , Gunnar Braun , Andreas Andreas , Rainer Leupers , Oliver Schliebusch , Heinrich Meyr, Instruction encoding synthesis for architecture exploration using hierarchical processor models, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Huynh Phung Huynh , Joon Edward Sim , Tulika Mitra, An efficient framework for dynamic reconfiguration of instruction-set customization, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
|
|
|
|
|