A delay metric for RC circuits based on the Weibull distribution

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A delay metric for RC circuits based on the Weibull distribution

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International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California

Pages: 620 - 624

Year of Publication: 2002

ISBN ~ ISSN:1092-3152 , 0-7803-7607-2

Authors

Frank Liu	IBM Austin, Austin, TX
Chandramouli Kashyap	IBM Austin, Austin, TX
Charles J. Alpert	IBM Austin, Austin, TX

Sponsors

: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 8, Downloads (12 Months): 29, Citation Count: 19

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ABSTRACT

Physical design optimizations such as placement, interconnect synthesis, oorplanning, and routing require fast and accurate analysis of RC networks. Because of its simple close form and fast evaluation, the Elmore delay metric has been widely adopted. The recently proposed delay metrics PRIMO and H-gamma match the rst three circuit moments to the probability density function of a Gamma statistical distribution. Although these methods demonstrate impressive accuracy compared to other delay metrics, their implementations tend to be challenging. As an alternative to matching to the Gamma distribution, we propose to match the rst two circuit moments to a Weibull distribution. The result is a new delay metric called Weibull based Delay (WED). The primary advantages of WED over PRIMO and H-gamma are its efciency and ease of implementation. Experiments show that WED is robust and has satisfactory accuracies at both near and far-end nodes.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	Chandramouli V. Kashyap , Charles J. Alpert , Frank Liu , Anirudh Devgan, PERI: a technique for extending delay and slew metrics to ramp inputs, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Kanak Agarwal , Dennis Sylvester , David Blaauw, Simple metrics for slew rate of RC circuits based on two circuit moments, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Kanak Agarwal , Dennis Sylvester , David Blaauw , Frank Liu , Sani Nassif , Sarma Vrudhula, Variational delay metrics for interconnect timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Soroush Abbaspour , Hanif Fatemi , Massoud Pedram, VITA: variation-aware interconnect timing analysis for symmetric and skewed sources of variation considering variational ramp input, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Arif Ishaq Abou-Seido , Brian Nowak , Chris Chu, Fitted Elmore delay: a simple and accurate interconnect delay model, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.691-696, July 2004
	Chandramouli V. Kashyap , Charles J. Alpert , Frank Liu , Anirudh Devgan, Closed form expressions for extending step delay and slew metrics to ramp inputs, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Chirayu S. Amin , Yehea I. Ismail , Florentin Dartu, Piece-wise approximations of RLCK circuit responses using moment matching, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Uday Padmanabhan , Janet M. Wang , Jiang Hu, Statistical clock tree routing for robustness to process variations, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Anand Ramalingam , Sreekumar V. Kodakara , Anirudh Devgan , David Z. Pan, Robust analytical gate delay modeling for low voltage circuits, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Y. I. Ismail , C. S. Amin, Computation of signal threshold crossing times directly from higher order moments, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.246-253, November 07-11, 2004
	M. Mondal , Y. Massoud, Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.691-696, November 06-10, 2005, San Jose, CA
	Praveen Ghanta , Sarma Vrudhula, Variational Interconnect Delay Metrics for Statistical Timing Analysis, Proceedings of the 7th International Symposium on Quality Electronic Design, p.19-24, March 27-29, 2006
	Dinesh Pamunuwa , Shauki Elassaad , Hannu Tenhunen, Analytic Modeling of Interconnects for Deep Sub-Micron Circuits, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.835, November 09-13, 2003
	Chirayu S. Amin , Florentin Dartu , Yehea I. Ismail, Weibull Based Analytical Waveform Model, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.161, November 09-13, 2003
	Kanak Agarwal , Frank Liu, Efficient computation of current flow in signal wires for reliability analysis, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
	Soroush Abbaspour , Massoud Pedram , Amir Ajami , Chandramouli Kashyap, Fast interconnect and gate timing analysis for performance optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.14 n.12, p.1383-1388, December 2006
	Rajib Kar , Ashish K. Mal , Anup K. Bhattacharjee, An accurate slew metric for on-chip VLSI interconnect using Weibull distribution function, Proceedings of the International Conference on Advances in Computing, Communication and Control, January 23-24, 2009, Mumbai, India
	Peng Sun , Rong Luo, Closed-form solution for timing analysis of process variations on SWCNT interconnect, Proceedings of the 11th international workshop on System level interconnect prediction, July 26-27, 2009, San Francisco, CA, USA