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Combinational equivalence checking through function transformation
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 526 - 533  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Hee Hwan Kwak  Synopsys, Inc.
In-Ho Moon  Synopsys, Inc.
James H. Kukula  Synopsys, Inc.
Thomas R. Shiple  Synopsys, Inc.
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 13,   Citation Count: 2
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ABSTRACT

Circuits can be simplified for combinational equivalence checking by transforming internal functions, while preserving their ranges. In this paper, we investigate how to effiectively apply the idea to improve equivalence checking. We propose new heuristics to identify groups of nets in a cut, and elaborate detailed aspects of the new equivalence checking method. With a given miter, we identify a group of nets in a cut and transform the function of each net into a more compact representation with less variables. These new compact parametric representations preserve the range of nets as well as of the cut. This transformation significantly reduces the size of intermediate BDDs and enables the verification to be conclusive for many designs which state-of-the-art equivalence checkers fail to verify. Iterative groupings and transformations are performed until no grouping is possible for a cut. Then we proceed to the next cut and continue until the compare point is reached. Our experimental results show the effiectiveness of our strategy and new grouping heuristics on the new method.


REFERENCES

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E. Cerny and C. Mauras. Tautology checking using cross-controllability and cross-observability relations. In Proceedings of the International Conference on Computer-Aided Design, pages 34--37, Santa Clara, CA, Nov. 1990.
 
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O. Coudert, C. Berthet, and J. C. Madre. Verification of sequential machines using Boolean functional vectors. In L. Claesen, editor, Proceedings IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pages 111--128, Leuven, Belgium, Nov. 1989.
 
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Collaborative Colleagues:
Hee Hwan Kwak: colleagues
In-Ho Moon: colleagues
James H. Kukula: colleagues
Thomas R. Shiple: colleagues