| Combinational equivalence checking through function transformation |
| Full text |
Pdf
(297 KB)
|
| Source
|
International Conference on Computer Aided Design
archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California
Pages: 526 - 533
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 5, Downloads (12 Months): 13, Citation Count: 2
|
|
|
ABSTRACT
Circuits can be simplified for combinational equivalence checking by transforming internal functions, while preserving their ranges. In this paper, we investigate how to effiectively apply the idea to improve equivalence checking. We propose new heuristics to identify groups of nets in a cut, and elaborate detailed aspects of the new equivalence checking method. With a given miter, we identify a group of nets in a cut and transform the function of each net into a more compact representation with less variables. These new compact parametric representations preserve the range of nets as well as of the cut. This transformation significantly reduces the size of intermediate BDDs and enables the verification to be conclusive for many designs which state-of-the-art equivalence checkers fail to verify. Iterative groupings and transformations are performed until no grouping is possible for a cut. Then we proceed to the next cut and continue until the compare point is reached. Our experimental results show the effiectiveness of our strategy and new grouping heuristics on the new method.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
 |
1
|
Mark D. Aagaard , Robert B. Jones , Carl-Johan H. Serger, Formal verification using parametric representations of Boolean constraints, Proceedings of the 36th ACM/IEEE conference on Design automation, p.402-407, June 21-25, 1999, New Orleans, Louisiana, United States
[doi> 10.1145/309847.309968]
|
| |
2
|
|
| |
3
|
|
 |
4
|
|
| |
5
|
E. Cerny and C. Mauras. Tautology checking using cross-controllability and cross-observability relations. In Proceedings of the International Conference on Computer-Aided Design, pages 34--37, Santa Clara, CA, Nov. 1990.
|
| |
6
|
O. Coudert, C. Berthet, and J. C. Madre. Verification of sequential machines using Boolean functional vectors. In L. Claesen, editor, Proceedings IFIP International Workshop on Applied Formal Methods for Correct VLSI Design, pages 111--128, Leuven, Belgium, Nov. 1989.
|
| |
7
|
|
 |
8
|
|
| |
9
|
|
| |
10
|
|
 |
11
|
|
| |
12
|
|
 |
13
|
In-Ho Moon , James H. Kukula , Kavita Ravi , Fabio Somenzi, To split or to conjoin: the question in image computation, Proceedings of the 37th conference on Design automation, p.23-28, June 05-09, 2000, Los Angeles, California, United States
[doi> 10.1145/337292.337305]
|
| |
14
|
|
| |
15
|
|
| |
16
|
|
CITED BY 2
|
|
Jun Yuan , Ken Albin , Adnan Aziz , Carl Pixley, Constraint synthesis for environment modeling in functional verification, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
|
|
|
|
|