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ABSTRACT
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification problems can be formulated as QBF instances. A closely related research area to QBF is Boolean Satisfiability (SAT). Recent advances in SAT research have resulted in some very efficient SAT solvers. One of the critical techniques employed in these solvers is Conflict Driven Learning. In this paper, we adapt conflict driven learning for application in a QBF setting. We show that conflict driven learning can be regarded as a resolution process on the clauses. We prove that under certain conditions, tautology clauses obtained from resolution in QBF also obey the rules for implication and conflicts of regular (non-tautology) clauses; and therefore they can be treated as regular clauses and used in future search. We have implemented this idea in a new QBF solver called Quaffle and our initial experiments show that conflict driven learning can greatly speed up the solution process for most of the benchmarks we tested.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/378239.379017]
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J. Rintanen's benchmark suites are available at <u>http://www.informatik.uni-freiburg.de/~rintanen/qbf.html</u>
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More detailed and expanded experimental results are available at <u>http://ee.princeton.edu/~chaff/Quaffle.php</u>
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Enrico Giunchiglia , Massimo Narizzano , Armando Tacchella, Learning for quantified boolean logic satisfiability, Eighteenth national conference on Artificial intelligence, p.649-654, July 28-August 01, 2002, Edmonton, Alberta, Canada
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CITED BY 15
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G. Parthasarathy , M. K. Iyer , K.-T. Cheng , Li. C. Wang, Efficient reachability checking using sequential SAT, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.418-423, January 27-30, 2004, Yokohama, Japan
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Hratch Mangassarian , Andreas Veneris , Sean Safarpour , Marco Benedetti , Duncan Smith, A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California
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M. F. Ali , S. Safarpour , A. Veneris , M. S. Abadir , R. Drechsler, Post-verification debugging of hierarchical designs, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.871-876, November 06-10, 2005, San Jose, CA
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Marco Maratea , Francesco Ricca , Wolfgang Faber , Nicola Leone, Look-back techniques and heuristics in DLV: Implementation, evaluation, and comparison to QBF solvers, Journal of Algorithms, v.63 n.1-3, p.70-89, January, 2008
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