Molecular electronics: devices, systems and tools for gigagate, gigabit chips

ABSTRACT

New electronics technologies are emerging which may carry us beyond the limits of lithographic processing down to molecular-scale feature sizes. Devices and interconnects can be made from a variety of molecules and materials including bistable and switchable organic molecules, carbon nanotubes, and, single-crystal semiconductor nanowires. They can be self-assembled into organized structures and attached onto lithographic substrates. This tutorial reviews emerging molecular-scale electronics technology for CAD and system designers and highlights where ICCAD research can help support this technology.

REFERENCES

• 1: Semiconductor Industry Association, "Int'l Technology Roadmap for Semiconductors," http://public.itrs.net/Files/2001ITRS/Home.htm, 2001.
• 2: Jonathan Babb , Martin Rinard , Csaba Andras Moritz , Walter Lee , Matthew Frank , Rajeev Barua , Saman Amarasinghe, Parallelizing Applications into Silicon, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.70, April 21-23, 1999
• 3: P. Bricaud and M. Keating, "IP Reuse Creation for System-on-a-Chip Design," in Proceedings of the 1999 IEEE Custom Integrated Circuits Conference, 1999.
• 4: M. Budiu, "Application-Specific Hardware: Computing Without CPUs," in 4th CMU Symposium on Computer Systems SOCS-4, October 2001, also CMU Technical Report CMU-CS-01-164.
• 5: Eylon Caspi , Michael Chu , Randy Huang , Joseph Yeh , John Wawrzynek , André DeHon, Stream Computations Organized for Reconfigurable Execution (SCORE), Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications, p.605-614, August 27-30, 2000
• 6: J. Chen, M. Reed, A. Rawlett, and J. Tour, "Large On-Off Ratios and Negative Differential Resistance in a Molecular Electronic Device," Science, vol. 286, pp. 1550, 1999.
• 7: J. Chen, W. Wang, M. A. Reed, M. Rawlett, D. W. Price, and J. M. Tour, "Room-Temperature Negative Differential Resistance in Nanoscale Molecular Junctions," Appl. Phys. Lett., vol. 77, pp. 1224, 2000.
• 8: C. Collier, G. Mattersteig, E. Wong, Y. Luo, K. Beverly, J. Sampaio, F. Raymo, J. Stoddart, and J. Heath, "A {2}Catenane-Based Solid State Reconfigurable Switch," Science, vol. 289, pp. 1172--1175, 2000.
• 9: P. Collins, M. Arnold, and Ph. Avouris, "Engineering Carbon Nanotubes and Nanotube Circuits Using Electrical Breakdown," Science, vol. 292, pp. 706, 2001.
• 10: Y. Cui, X. Duan, J. Hu, and C. Lieber, "Doping and electrical transport in silicon nanowires," Journal of Physical Chemistry B, vol. 104, no. 22, pp. 5213--5216, 2000.
• 11: Y. Cui and C. Lieber, "Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks," Science, vol. 291, pp. 851, 2001.
• 12: Y. Cui, C. Lieber, L. Lauhon, M. Gudiksen, and J. Wang, "Diameter-controlled synthesis of single crystal silicon nanowires," Applied Physics Lett., vol. 78, no. 15, pp. 2214--2216, 2001.
• 13: W. B. Culbertson , R. Amerson , R. J. Carter , P. Kuekes , G. Snider, Defect tolerance on the Teramac custom computer, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.116, April 16-18, 1997
• 14: P. D. Franzon D. P. Nackashi, "Molectronics: A circuit design perspective," in Proc. of the SPIE, 2002, vol. 4236.
• 15: A. DeHon, "Array-Based Architecture for Molecular Electronics," in Proceedings of the First Workshop on Non-Silicon Computation (NSC-1), February 2002.
• 16: André DeHon , Randy Huang , John Wawrzynek, Hardware-Assisted Fast Routing, Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.205, September 22-24, 2002
• 17: J. C. Ellenbogen and J. C. Love, "Architectures for molecular electronic computers: 1. Logic structures and an adder designed from molecular electronic diodes," Proc. IEEE, vol. 88, no. 3, pp. 386--426, 2000.
• 18: Daniel D. Gajski , Nikil D. Dutt , Allen C.-H. Wu , Steve Y.-L. Lin, High-level synthesis: introduction to chip and system design, Kluwer Academic Publishers, Norwell, MA, 1992
• 19: Seth Copen Goldstein , Mihai Budiu, NanoFabrics: spatial computing using molecular electronics, Proceedings of the 28th annual international symposium on Computer architecture, p.178-191, June 30-July 04, 2001, Göteborg, Sweden
• 20: S. Goldstein and D. Rosewater, "Digital Logic Using Molecular Electronics," in Int'l Solid State Circuits Conference, Feb. 2002.
• 21: Y. Huang, X. Duan, Y. Cui, L. Lauhon, K-H. Kim, and C. Lieber, "Logic Gates and Computation from Assembled Nanowire Building Blocks," Science, vol. 294, pp. 1313, 2001.
• 22: Y. Huang, X. Duan, Q. Wei, and C. Lieber, "Directed assembly of onedimensional nanostructures into functional networks," Science, vol. 291, pp. 630--633, January 2001.
• 23: S. Husband, C. Husband, Price, Dirk, Franzon, Seminario, and Reed, "The Nanocell Approach to a Molecular Computer," Moletronics PI Meeting.
• 24: S. Iijima, "Helical Microtubules of Graphitic Carbon," Nature, vol. 354, pp. 56, 1991.
• 25: T. I. Kamins, R. S. Williams, Y. Chen, Y.-L. Chang, and Y. A. Chang, "Chemical vapor deposition of Si nanowires nucleated by TiSi2 islands on Si," Applied Physics Letters, vol. 76, no. 562, 2000.
• 26: R. Landauer, "Spatial Variation of Current and Fields Due to Localized Scatterers in Metallic Conduction," IBM Journal of Research and Development, vol. 1, no. 3, 1957.
• 27: Philippe Magarshack, Improving SoC Design Quality through a Reproducible Design Flow, IEEE Design & Test, v.19 n.1, p.76-83, January 2002 [doi>10.1109/54.980055]
• 28: J. K. N. Mbindyo, B. R. Reiss, B. R. Martin, C. D. Keating, M. J. Natan, and T. E. Mallouk, "DNA-Directed Assembly of Gold Nanowires on Complementary Surfaces," Advanced Materials, vol. 13, pp. 249--254, 2001.
• 29: C. Mirkin, "Programming the Assembly of Two- and Three-Dimensional Architectures with DNA and Nanoscale Inorganic Building Blocks," Inorg. Chem., vol. 39, pp. 2258--72, 2000.
• 30: M. Mishra and S. C. Goldstein, "Scalable Defect Tolerance for Molecular Electronics," in First Workshop on Non-Silicon Computing, Cambridge, MA, February 2002.
• 31: A. Morales and C. Lieber, "A laser ablation method for the synthesis of crystalline semiconductor nanowires," Science, vol. 279, pp. 208--211, 1998.
• 32: J. Von Neumann, "Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components," in Automata Studies, C. Shannon and J. McCarthy, Eds. Princeton University Press, 1956.
• 33: D. J. Pena, B. Razavi, P. A. Smith, M. J. Natan, T. S. Mayer, T. E. Mallouk, and C. D. Keating, "Electrochemical Synthesis of Multi-Material Nanowires as Building Blocks for Functional Nanostructures," in MRS Symposium Proceedings, 2001, vol. 636, pp. D4.6.1--4.6.6.
• 34: T. Rueckes, K. Kim, E. Joselevich, G. Tseng, C. Cheung, and C. Lieber, "Carbon nanotube based nonvolatile random access memory for molecular computing," Science, vol. 289, pp. 94--97, 2000.
• 35: R. Service, "Assembling Nanocircuits From the Bottom Up," Science, vol. 293, pp. 782, 2001.
• 36: H. Soh, C. Quate, A. Morpurgo, C. Marcus, J. Kong, and H. Dai, "Integrated nanotube circuits: Controlled growth and ohmic contacting of single-walled carbon nanotubes," Applied Physics Letters, vol. 75, no. 5, 1999.
• 37: D. A. Spielman, Highly fault-tolerant parallel computation, Proceedings of the 37th Annual Symposium on Foundations of Computer Science, p.154, October 14-16, 1996
• 38: Dennis Sylvester , Kurt Keutzer, Rethinking Deep-Submicron Circuit Design, Computer, v.32 n.11, p.25-33, November 1999 [doi>10.1109/2.803637]
• 39: S. Williams and P. Kuekes, "Demultiplexer for a Molecular Wire Crossbar Network," United States Patent Number: 6,256,767, July 3 2001.
• 40: S. Williams, P. Kuekes, and J. R. Heath, "Molecular-Wire Crossbar Interconnect (MWCI) for Signal Routing and Communications," US Patent 6,314,019, November 6, 2001.
• 41: E. Winfree, F. Liu, L. A. Wenzler, and N. C. Seeman, "Design and Self-Assembly of Two-Dimensional DNA Crystals," Nature, vol. 394, pp. 539--544, 1998.
• 42: Y. Xia, J. Rogers, K. Paul, and G. Whitesides, "Unconventional Methods for Fabricating and Patterning Nanostructures," Chem. Rev., vol. 99, pp. 823--1848, 1999.
• 43: C. Zhou, M. R. Deshpande, M. A. Reed, and J. M. Jones II, L. anmd Tour, "Nanoscale Metal/Self-Assembled Monolayer/Metal Heterostructures," Appl. Phys. Lett, vol. 71, pp. 611, 1997.
• 44: C. Zhou, C. J. Muller, M. R. Deshpande, J. W. Sleight, and M. A. Reed, "Microfabrication of a mechanically controllable break junction in silicon," Applied Physics Letters, vol. 67, pp. 1160, 1995.

INDEX TERMS

Primary Classification:
  J. Computer Applications
  J.6 COMPUTER-AIDED ENGINEERING
      Subjects: Computer-aided design (CAD)

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.1 Semiconductor Memories
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Arithmetic and logic units

  J. Computer Applications
  J.2 PHYSICAL SCIENCES AND ENGINEERING
      Subjects: Electronics

General Terms:
Design, Theory