Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects

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Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects

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International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California

Pages: 280 - 284

Year of Publication: 2002

ISBN ~ ISSN:1092-3152 , 0-7803-7607-2

Authors

Harshit Shah	Georgia Institute of Technology, Atlanta, GA
Pun Shiu	Georgia Institute of Technology, Atlanta, GA
Brian Bell	Georgia Institute of Technology, Atlanta, GA
Mamie Aldredge	Georgia Institute of Technology, Atlanta, GA
Namarata Sopory	Georgia Institute of Technology, Atlanta, GA
Jeff Davis

Sponsors

: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 15, Downloads (12 Months): 50, Citation Count: 7

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ABSTRACT

As technology advances towards billion transistor systems, the cost of complex wire networks will require area efficient wiring methodologies. This paper explores the tradeoffs between wire latency, throughput and area for deep submicron (DSM) interconnect technologies. From basic physical models, optimal wiring sizing for repeater networks are rigorously derived and compared to HSPICE simulations. Key case studies from 250nm to 70nm technologies reveal that significant wire area reduction (20--50%) can be achieved with optimal wire sizing to maximize the throughput per unit wire area.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 7

	Lizheng Zhang , Yuhen Hu , Charlie, Chungping Chen, Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Lizheng Zhang , Yuhen Hu , Charlie Chung-Ping Chen, Wave-pipelined on-chip global interconnect, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Terrence Mak , Crescenzo D'Alessandro , Pete Sedcole , Peter Y. K. Cheung , Alex Yakovlev , Wayne Luk, Global interconnections in FPGAs: modeling and performance analysis, Proceedings of the 2008 international workshop on System level interconnect prediction, April 05-08, 2008, Newcastle, United Kingdom
	Nevin Kirman , Meyrem Kirman , Rajeev K. Dokania , Jose F. Martinez , Alyssa B. Apsel , Matthew A. Watkins , David H. Albonesi, Leveraging Optical Technology in Future Bus-based Chip Multiprocessors, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.492-503, December 09-13, 2006
	Basel Halak , Alex Yakovlev, Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods, Proceedings of the conference on Design, automation and test in Europe, March 10-14, 2008, Munich, Germany
	DiaaEldin Khalil , Yehea Ismail, A global interconnect link design for many-core microprocessors, Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, November 24-25, 2008, Cairo, Egypt
	Shuming Chen , Xiangyuan Liu, A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs, Proceedings of the First International Symposium on Networks-on-Chip, p.75-82, May 07-09, 2007