A local circuit topology for inductive parasitics

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A local circuit topology for inductive parasitics

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International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California

Pages: 208 - 214

Year of Publication: 2002

ISBN ~ ISSN:1092-3152 , 0-7803-7607-2

Author

Andrea Pacelli

State University of New York at Stony Brook, Stony Brook, NY

Sponsors

: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 4, Downloads (12 Months): 14, Citation Count: 5

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ABSTRACT

A novel circuit topology for inductive coupling between interconnecting wires is presented. The model is local, i.e., only coupling between neighboring wires is explicitly modeled. However, the topology accounts for long-range coupling by propagating the vector potential from one wire to the next. Examples of model calibration, both directly from layout and as model-order reduction of a given inductance matrix, are presented for simple wiring structures.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 5

	Clement Luk , Tsung-Hao Chen , Charlie C.-P. Chen, Frequency-dependent reluctance extraction, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.792-797, January 27-30, 2004, Yokohama, Japan
	Satrajit Gupta , Lawrence T. Pileggi, CHIME: coupled hierarchical inductance model evaluation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Jitesh Jain , Stephen Cauley , Cheng-Kok Koh , Venkataramanan Balakrishnan, SASIMI: sparsity-aware simulation of interconnect-dominated circuits with non-linear devices, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Hao Yu , Lei He, Vector potential equivalent circuit based on PEEC inversion, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Yu Du , Wayne Dai, Partial reluctance based circuit simulation is efficient and stable, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China