Sub-90nm technologies

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Sub-90nm technologies: challenges and opportunities for CAD

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International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California

Pages: 203 - 206

Year of Publication: 2002

ISBN ~ ISSN:1092-3152 , 0-7803-7607-2

Authors

Tanay Karnik	Intel Labs, Hillsboro, OR
Shekhar Borkar	Intel Labs, Hillsboro, OR
Vivek De	Intel Labs, Hillsboro, OR

Sponsors

: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 13, Downloads (12 Months): 74, Citation Count: 22

Additional Information:

appendices and supplements abstract references cited by index terms collaborative colleagues

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APPENDICES and SUPPLEMENTS

a203-karnik.zip (48.11 MB)

Presentations from the 2002 ICCAD conference: Innovative design challenges

ABSTRACT

Future high performance microprocessor design with technology scaling beyond 90nm will pose two major challenges: (1) energy and power, and (2) parameter variations. Design practice will have to change from deterministic design to probabilistic and statistical design. This paper discusses circuit techniques and design automation opportunities to overcome the challenges.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Pollack F., New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies; Micro32, 1999.
	2	George Sery , Shekhar Borkar , Vivek De, Life is CMOS: why chase the life after?, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.513941]
	3	Tanay Karnik , Yibin Ye , James Tschanz , Liqiong Wei , Steven Burns , Venkatesh Govindarajulu , Vivek De , Shekhar Borkar, Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514042]
	4	Tschanz, J., et al., "Design optimizations of a high performance microprocessor using combinations of dual-Vt allocation and transistor sizing", VLSI Circuits Symposium 2001, pp. 218--219.
	5	Pankaj Pant , Rabindra K. Roy , Abhijit Chatterjee, Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.2, p.390-394, April 2001 [doi>10.1109/92.924061]
	6	Liqiong Wei , Zhanping Chen , Kaushik Roy , Mark C. Johnson , Yibin Ye , Vivek K. De, Design and optimization of dual-threshold circuits for low-voltage low-power applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.1, p.16-24, March 1999 [doi>10.1109/92.748196]
	7	Mohab Anis , Mohamed Mahmoud , Mohamed Elmasry , Shawki Areibi, Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA [doi>10.1145/513918.514041]
	8	Kuroda, T., et al., Low-power CMOS digital design with dual embedded adaptive power supplies. JSSC, Vol. 35, Issue 4, April 2000, pp. 652--655.
	9	Krishnamurthy, R., et al., High-performance and low-power challenges for sub-70nm microprocessor circuits. CICC 2002, pp. 125--128.
	10	Keshavarzi, A., et al., Forward body bias for uPs in 130nm technology generation and beyond. VLSI Circuits Symp. 2002, pp. 125--128.

CITED BY 22

	Jingjing Fu , Zuying Luo , Xianlong Hong , Yici Cai , Sheldon X.-D. Tan , Zhu Pan, VLSI on-chip power/ground network optimization considering decap leakage currents, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Imad A. Ferzli , Farid N. Najm, Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Shekhar Borkar , Tanay Karnik , Vivek De, Design and reliability challenges in nanometer technologies, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Tudor Dumitras , Sam Kerner , Radu Marculescu, Enabling on-chip diversity through architectural communication design, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.799-805, January 27-30, 2004, Yokohama, Japan
	Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Ashish Srivastava , Saumil Shah , Kanak Agarwal , Dennis Sylvester , David Blaauw , Stephen Director, Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Jason Cong , Ashok Jagannathan , Glenn Reinman , Yuval Tamir, Understanding the energy efficiency of SMT and CMP with multiclustering, Proceedings of the 2005 international symposium on Low power electronics and design, August 08-10, 2005, San Diego, CA, USA
	Luca Benini, Advanced power management techniques: going beyond intelligent shutdown, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Chirayu Amin , Chandramouli Kashyap , Noel Menezes , Kip Killpack , Eli Chiprout, A multi-port current source model for multiple-input switching effects in CMOS library cells, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	Wei Wang , Yu Hu , Yin-He Han , Xiao-Wei Li , You-Sheng Zhang, Leakage current optimization techniques during test based on don't care bits assignment, Journal of Computer Science and Technology, v.22 n.5, p.673-680, September 2007
	Mark Hempstead , Gu-Yeon Wei , David Brooks, Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generations, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
	Joonsoo Kim , Michael Orshansky, Towards formal probabilistic power-performance design space exploration, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Wei Li , Daniel Blakely , Scott Van Sooy , Keven Dunn , David Kidd , Robert Rogenmoser , Dian Zhou, LVS verification across multiple power domains for a quad-core microprocessor, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.2, p.490-500, April 2006
	Sarvesh Bhardwaj , Sarma Vrudhula, Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.713-718, November 06-10, 2005, San Jose, CA
	K. Chopra , S. Shah , A. Srivastava , D. Blaauw , D. Sylvester, Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.1023-1028, November 06-10, 2005, San Jose, CA
	Imad A. Ferzli , Farid N. Najm, Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.770, November 09-13, 2003
	Bill Grundmann , Rajesh Galivanche , Sandip Kundu, Circuit and Platform Design Challenges in Technologies beyond 90nm, Proceedings of the conference on Design, Automation and Test in Europe, p.10044, March 03-07, 2003
	Twan Basten , Luca Benini , Anantha Chandrakasan , Menno Lindwer , Jie Liu , Rex Min , Feng Zhao, Scaling into Ambient Intelligence, Proceedings of the conference on Design, Automation and Test in Europe, p.10076, March 03-07, 2003
	Yi-Ping You , Chung-Wen Huang , Jenq Kuen Lee, Compilation for compact power-gating controls, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.4, p.51-es, September 2007
	Animesh Datta , Swarup Bhunia , Jung Hwan Choi , Saibal Mukhopadhyay , Kaushik Roy, Profit aware circuit design under process variations considering speed binning, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.16 n.7, p.806-815, July 2008
	Charbel J. Akl , Magdy A. Bayoumi, Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion, Proceeding of the thirteenth international symposium on Low power electronics and design, August 11-13, 2008, Bangalore, India
	Qiang Zhou , Xin Zhao , Yici Cai , Xianlong Hong, An MTCMOS technology for low-power physical design, Integration, the VLSI Journal, v.42 n.3, p.340-345, June, 2009