Managing power and performance for System-on-Chip designs using Voltage Islands

ABSTRACT

This paper discusses Voltage Islands, a system architecture and chip implementation methodology, that can be used to dramatically reduce active and static power consumption for System-on-Chip (SoC) designs. As technology scales for increased circuit density and performance, the need to reduce power consumption increases in significance as designers strive to utilize the advancing silicon capabilities. The consumer product market further drives the need to minimize chip power consumption.Effective use of Voltage Islands for meeting SoC power and performance requirements, while meeting Time to Market (TAT) demands, requires novel approaches throughout the design flow as well as special circuit components and chip powering structures. This paper outlines methods being used today to design Voltage Islands in a rapid-TAT product development environment, and discusses the need for industry EDA advances to create an industry-wide Voltage Island design capability.

REFERENCES

• 1: Enomoto, E., "Low Power Design Technology for Digital LSIs," IEICE Transactions on Electronics v E79-C n 12, Dec. 1996, pp 1639--1649.
• 2: Fred J. Pollack, New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only), Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture, p.2, November 16-18, 1999, Haifa, Israel
• 3: Shekhar Borkar, Design Challenges of Technology Scaling, IEEE Micro, v.19 n.4, p.23-29, July 1999 [doi>10.1109/40.782564]
• 4: Adan, A.O. and Higashi K., "OFF-State Leakage Current Mechanisms in BulkSi and SOI MOSFETs and Their Impact on CMOS ULSIs Standby Current," IEEE Transactions on Electron Devices, Vol. 48, No. 9, Sept. 2001, pp 2050--2057.
• 5: Stathis, J.H., "Physical and Predictive Models of Ultra Thin Oxide Reliability in CMOS Devices and Circuits," IEEE 39th Annual International Reliability Physics Symposium, Orlando, Florida, 2001, pp 132--149.
• 6: Nowack, E.J., "Maintaining the Benefits of CMOS Scaling when Scaling Bogs Down," IBM Journal of Research and Development, No. 2/3 March/May 2002.
• 7: Gary, S., "Low Power Microprocessor Design," Low Power Design Methodologies, Kluwer Academic Publishers, 1996, pp 279--281.
• 8: "IC Wizard - The Hierarchical Design Planning Tool," © 2002 Monterey Design Systems, Inc., http://www.mondes.com/prod_icw.html
• 9: "TeraForm® RTL Design Planner for Deep Submicron SOCs," © 2002 Tera Systems, Inc., http://www.terasystems.com/ products/datasheet.htm
• 10: "First Encounter," © 2002 Cadence Design Systems, Inc., http://www.cadence.com/products/first_encounter.html
• 11: 1481--1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System, copyright 1999 by IEEE.
• 12: Stephen V. Kosonocky , Mike Immediato , Peter Cottrell , Terence Hook , Randy Mann , Jeff Brown, Enchanced multi-threshold (MTCMOS) circuits using variable well bias, Proceedings of the 2001 international symposium on Low power electronics and design, p.165-169, August 2001, Huntington Beach, California, United States [doi>10.1145/383082.383125]
• 13: Sani R. Nassif , Joseph N. Kozhaya, Fast power grid simulation, Proceedings of the 37th conference on Design automation, p.156-161, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337359]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: System architectures

Additional Classification:
  D. Software
  D.2 SOFTWARE ENGINEERING
      D.2.1 Requirements/Specifications
          Subjects: Methodologies (e.g., object-oriented, structured)

General Terms:
Experimentation, Performance, Theory