A hybrid ASIC and FPGA architecture

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A hybrid ASIC and FPGA architecture

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International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California

Pages: 187 - 194

Year of Publication: 2002

ISBN ~ ISSN:1092-3152 , 0-7803-7607-2

Authors

Paul S. Zuchowski	IBM Microelectronics Division, Essex Junction, Vermont
Christopher B. Reynolds	IBM Microelectronics Division, Essex Junction, Vermont
Richard J. Grupp	IBM Microelectronics Division, Essex Junction, Vermont
Shelly G. Davis	Xilinx Corporation, San Jose, California,
Brendan Cremen	Xilinx Corporation, Dublin, Ireland
Bill Troxel	Xilinx Corporation, Boulder, Colorado

Sponsors

: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 14, Downloads (12 Months): 96, Citation Count: 20

Additional Information:

appendices and supplements references cited by index terms collaborative colleagues

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DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/774572.774600 What is a DOI?

APPENDICES and SUPPLEMENTS

a187-zuchowski.zip (61.32 MB)

Presentations from the 2002 ICCAD conference: Innovative design challenges

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	IBM Microelectronics, SA-12E Databook, April 2002.
	2	IBM Microelectronics, ASIC SA-12E Standard Cell/Gate Array Product Brief, June 2002.
	3	IBM Microelectronics, SA-27E Databook : Base Library and I/Os, July 2002.
	4	IBM Microelectronics, Blue Logic SA-27E ASIC Product Brief, June 2002.
	5	IBM Microelectronics, Cu-11 Databook: 12-Track Base Library, June 2002.
	6	IBM Microelectronics, Blue Logic Cu-11 ASIC Product Brief, June 2002.
	7	IBM Microelectronics, Blue Logic Cu-08 ASIC Product Brief, April 2002.
	8	Xilinx Corporation, XC4000E and XC4000X Series Field-Programmable Gate Arrays, Version 1.6, May 1999.
	9	Xilinx Corporation, Virtextm 2.5V Field Programmable Gate Arrays DS003-1, Version 2.5, April 2001.
	10	Xilinx Corporation, Virtex-II 1.5V Field Programmable Gate Arrays DS031-1, Version 2.5, April 2001.
	11	G.R. Goslin, "A guide to using FPGAS for Application Specific Digital System Processing Performance", Xilinx Corporation, 1995.
	12	Semico, "Foundry Wafer Pricing: Fourth Quarter 2001"
	13	David E. Lackey , Paul S. Zuchowski , Thomas R. Bednar , Douglas W. Stout , Scott W. Gould , John M. Cohn, Managing power and performance for System-on-Chip designs using Voltage Islands, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.195-202, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774601]
	14	A.M. Rincon, M. Trick, T. Guzowski, "A proven Methodology for Designing One-Million-Gate ASICs," Proc. IEEE Custom Integrated Circuits Conference, pp. 44--52, May 1996.
	15	J. J. Engel , T. S. Guzowski , A. Hunt , D. E. Lackey , L. D. Pickup , R. A. Proctor , K. Reynolds , A. M. Rincon , D. R. Stauffer, Design methodology for IBM ASIC products, IBM Journal of Research and Development, v.40 n.4, p.387-406, July 1996
	16	K.M. Carrig, N.T. Gargiulo, R.P. Gregor, D.R. Menard, H.E. Reindel, "A New Direction in ASIC High-Performance Clock Methodology," Proc. IEEE Custom Integrated Circuits Conference, May 1998, pp. 593--596.
	17	Karen Parnell and Nick Mehta, "Programmable Logic Design Quick Start Hand Book," Second Edition, Jan. 2002.
	18	W. E. Donath "Logic Partitioning in Physical Design Automation of VLSI Systems," The Benjamin/Cummings Publisher Company, 1988.
	19	International Technology Roadmap for Semiconductors (ITRS) 2000.
	20	Helena Krupnova , Ali Abbara , Gabrièle Saucier, A hierarchy-driven FPGA partitioning method, Proceedings of the 34th annual conference on Design automation, p.522-525, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266271]
	21	"IC Wizard - The Hierarchical Design Planning Tool," © 2002 Monterey Design Systems, Inc., http://www.mondes.com/prod_icw.html
	22	"TeraForm® RTL Design Planner for Deep Submicron SOCs," © 2002 Tera Systems, Inc., <u>http://www.terasystems.com/products/datasheet.htm</u>
	23	"First Encounter," © 2002 Cadence Design Systems, Inc., http://www.cadence.com/products/first_encounter.html
	24	S. Wilton and R. Saleh, "Programmable Logic IP Cores in SoC Design: Opportunities and Challenges," IEEE Custom Integrated Circuits Conference, May 2001.

CITED BY 20

	Reinaldo A. Bergamaschi , John Cohn, The A to Z of SoCs, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.790-798, November 10-14, 2002, San Jose, California
	David E. Lackey , Paul S. Zuchowski , Juergen Koehl, Designing mega-ASICs in nanogate technologies, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Leon Stok , John Cohn, There is life left in ASICs, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Narendra V. Shenoy , Jamil Kawa , Raul Camposano, Design automation for mask programmable fabrics, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Navaratnasothie Selvakkumaran , Abhishek Ranjan , Salil Raje , George Karypis, Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Satish Sivaswamy , Gang Wang , Cristinel Ababei , Kia Bazargan , Ryan Kastner , Eli Bozorgzadeh, HARP: hard-wired routing pattern FPGAs, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	L. Pileggi , H. Schmit , A. J. Strojwas , P. Gopalakrishnan , V. Kheterpal , A. Koorapaty , C. Patel , V. Rovner , K. Y. Tong, Exploring regular fabrics to optimize the performance-cost trade-off, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Jennifer L. Wong , Farinaz Kourshanfar , Miodrag Potkonjak, Flexible ASIC: shared masking for multiple media processors, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Mingjie Lin , Abbas El Gamal , Yi-Chang Lu , Simon Wong, Performance benefits of monolithically stacked 3D-FPGA, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Luca Benini, Advanced power management techniques: going beyond intelligent shutdown, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Ian Kuon , Jonathan Rose, Measuring the gap between FPGAs and ASICs, Proceedings of the internation symposium on Field programmable gate arrays, February 22-24, 2006, Monterey, California, USA
	Hadi Parandeh-Afshar , Philip Brisk , Paolo Ienne, A novel FPGA logic block for improved arithmetic performance, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Hadi Parandeh-Afshar , Philip Brisk , Paolo Ienne, Efficient synthesis of compressor trees on FPGAs, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Deming Chen , Jason Cong , Peichen Pan, FPGA Design Automation: A Survey, Foundations and Trends® in Electronic Design Automation, v.1 n.3, p.139-169, January 2006
	Ian Kuon , Russell Tessier , Jonathan Rose, FPGA Architecture: Survey and Challenges, Foundations and Trends® in Electronic Design Automation, v.2 n.2, p.135-253, February 2008
	Mike Butts, Synchronization through Communication in a Massively Parallel Processor Array, IEEE Micro, v.27 n.5, p.32-40, September 2007
	Alessandro Cevrero , Panagiotis Athanasopoulos , Hadi Parandeh-Afshar , Ajay K. Verma , Philip Brisk , Frank K. Gurkaynak , Yusuf Leblebici , Paolo Ienne, Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA
	Heiko Hinkelmann , Peter Zipf , Jia Li , Guifang Liu , Manfred Glesner, On the design of reconfigurable multipliers for integer and Galois field multiplication, Microprocessors & Microsystems, v.33 n.1, p.2-12, February, 2009
	Alessandro Cevrero , Panagiotis Athanasopoulos , Hadi Parandeh-Afshar , Ajay K. Verma , Hosein Seyed Attarzadeh Niaki , Chrysostomos Nicopoulos , Frank K. Gurkaynak , Philip Brisk , Yusuf Leblebici , Paolo Ienne, Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.2 n.2, p.1-36, June 2009
	Kees Goossens , Martijn Bennebroek , Jae Young Hur , Muhammad Aqeel Wahlah, Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, p.45-54, April 07-10, 2008