Hardware/software partitioning of software binaries

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Hardware/software partitioning of software binaries

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International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California

Pages: 164 - 170

Year of Publication: 2002

ISBN ~ ISSN:1092-3152 , 0-7803-7607-2

Authors

Greg Stitt	University of California, Riverside
Frank Vahid	University of California, Riverside

Sponsors

: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 21, Downloads (12 Months): 70, Citation Count: 20

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

Partitioning an embedded system application among a microprocessor and custom hardware has been shown to improve the performance, power or energy of numerous examples. The advent of single-chip microprocessor/FPGA platforms makes such partitioning even more attractive. Previous partitioning approaches have partitioned sequential program source code, such as C or C++. We introduce a new approach that partitions at the software binary level. Although source code partitioning is preferable from a purely technical viewpoint, binary-level partitioning provides several very practical benefits for commercial acceptance. We demonstrate that binary-level partitioning yields competitive speedup results compared to source-level partitioning, achieving an average speedup of 1.4 compared to 1.5 for eight benchmarks partitioned on a single-chip microprocessor/FPGA device.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	G. Aigner, A. Diwan, D. Heine, M. Lam, D. Moore, B. Murphy, C. Sapuntzakis. An Overview of the SUIF2 Compiler Infrastructure. Computer Systems Laboratory, Standford University.
	2	Altera Corporation, ARM-Based Embedded Processor PLDs, August, 2001.
	3	Peter M. Athanas , Harvey F. Silverman, Processor reconfiguration through instruction-set metamorphosis, Computer, v.26 n.3, p.11-18, March 1993 [doi>10.1109/2.204677]
	4	Atmel FPSLIC, http://www.atmel.com/atmel/products/prod39.htm.
	5	Vasanth Bala , Evelyn Duesterwald , Sanjeev Banerjia, Dynamo: a transparent dynamic optimization system, Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, p.1-12, June 18-21, 2000, Vancouver, British Columbia, Canada
	6	A. Balboni , W. Fornaciari , D. Sciuto, Partitioning and Exploration Strategies in the TOSCA Co-Design Flow, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.62, March 18-20, 1996
	7	W. Böhm , J. Hammes , B. Draper , M. Chawathe , C. Ross , R. Rinker , W. Najjar, Mapping a Single Assignment Programming Language to Reconfigurable Systems, The Journal of Supercomputing, v.21 n.2, p.117-130, February 2002 [doi>10.1023/A:1013623303037]
	8	Kiran Bondalapati , Pedro C. Diniz , Phillip Duncan , John Granacki , Mary W. Hall , Rajeev Jain , Heidi Ziegler, DEFACTO: A Design Environment for Adaptive Computing Technology, Proceedings of the 11 IPPS/SPDP'99 Workshops Held in Conjunction with the 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing, p.570-578, April 12-16, 1999
	9	BRASS Research Group, http://brass.cs.berkeley.edu/.
	10	The Cameron Project, http://www.cs.colostate.edu/cameron/.
	11	C. Cifuentes, D. Simon, A. Fraboulet. Assembly to High-Level Language Translation. Department of Compter Science and Electrical Engineering, University of Queensland. Technical Report 439, August 1998.
	12	C. Cifuentes, M. Van Emmerik, D.Ung, D. Simon, T. Waddington. Preliminary Experiences with the Use of the UQBT Binary Translation Framework. Proceedings of the Workshop on Binary Translation, Newport Beach, USA, October 1999.
	13	P. Eles, Z. Peng, K. Kuchchinski and A. Doboli. System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search. Kluwer's Design Automation for Embedded Systems, vol2, no 1, pp. 5--32, Jan 1997.
	14	Rolf Ernst , Jorg Henkel , Thomas Benner, Hardware-Software Cosynthesis for Microcontrollers, IEEE Design & Test, v.10 n.4, p.64-75, October 1993 [doi>10.1109/54.245964]
	15	D.D. Gajski, F. Vahid, S. Narayan and J. Gong. SpecSyn: An Environment Supporting the Specify-Explore-Refine Paradigm for Hardware/Software System Design. IEEE Transactions on VLSI Systems, Vol. 6, No. 1, pp. 84--100, 1998.
	16	R. Goering. Compiler project marks Synopsys' step into post-ASIC world. EE Times, August 28, 2000, http://www.eedesign.com/story/OEG20000828S0020.
	17	T. Givargis and F. Vahid, The Platune Platform Tuning Environment, http://www.cs.ucr.edu/~dalton/Platune/, 2002.
	18	Maya B. Gokhale , Janice M. Stone, NAPA C: Compiling for a Hybrid RISC/FPGA Architecture, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.126, April 15-17, 1998
	19	J. R. Hauser , J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines, p.12, April 16-18, 1997
	20	Jörg Henkel , Rolf Ernst, A hardware/software partitioner using a dynamically determined granularity, Proceedings of the 34th annual conference on Design automation, p.691-696, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266323]
	21	Jouml;rg Henkel , Yanbing Li, Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder, Proceedings of the 6th international workshop on Hardware/software codesign, p.23-27, March 15-18, 1998, Seattle, Washington, United States
	22	Jörg Henkel, A low power hardware/software partitioning approach for core-based embedded systems, Proceedings of the 36th ACM/IEEE conference on Design automation, p.122-127, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309896]
	23	Intel StrongArm 1110 Processor, http://developer.intel.com/design/strong.
	24	Asawaree Kalavade , Edward A. Lee, A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem, Proceedings of the 3rd international workshop on Hardware/software co-design, September 22-24, 1994, Grenoble, France
	25	A. Klaiber. The Technology Behind Crusoe Processors. Transmeta Corporation White Paper, January 2000.
	26	Yanbing Li , Tim Callahan , Ervan Darnell , Randolph Harr , Uday Kurkure , Jon Stockwood, Hardware-software co-design of embedded reconfigurable architectures, Proceedings of the 37th conference on Design automation, p.507-512, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337559]
	27	Afzal Malik , Bill Moyer , Dan Cermak, A low power unified cache architecture providing power and performance flexibility (poster session), Proceedings of the 2000 international symposium on Low power electronics and design, p.241-243, July 25-27, 2000, Rapallo, Italy [doi>10.1145/344166.344610]
	28	MIPS Technologies, Inc., http://www.mips.com.
	29	Proceler, http://www.proceler.com.
	30	Rajesh K. Gupta , Giovanni De Micheli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design & Test, v.10 n.3, p.29-41, July 1993 [doi>10.1109/54.232470]
	31	C. Snyder. FPGA Processors Ready for Takeoff. Microprocessor Report, Novemeber 2000, pp. 25--29.
	32	Greg Stitt , Brian Grattan , Jason Villarreal , Frank Vahid, Using On-Chip Configurable Logic to Reduce Embedded System Software Energy, Proceedings of the 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p.143, September 22-24, 2002
	33	Triscend Corporation, http://www.triscend.com/. 2002.
	34	G. Vanmeerbeeck , P. Schaumont , S. Vernalde , M. Engels , I. Bolsens, Hardware/software partitioning of embedded system in OCAPI-xl, Proceedings of the ninth international symposium on Hardware/software codesign, p.30-35, April 2001, Copenhagen, Denmark [doi>10.1145/371636.371665]
	35	J. Villarreal, R. Lysecky, S. Cotterell, K. Miller and F. Vahid. Loop Analysis of Embedded Applications. UC Riverside Technical Report UCR-CSE-01-03, 2001.
	36	Virtex Power Estimator, http://support.xilinx.com/cgi-bin/powerweb.pl.
	37	M. Wan, Y. Ichikawa, D. Lidsky, J. Rabaey. An energy conscious methodology for early design exploration of heterogeneous DSPs. Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, p. 111--117, Santa Clara, May 1998.
	38	Xilinx Corporation, Virtex-II Pro Platform FPGA Handbook, January 31, 2002.

CITED BY 20

	Greg Stitt , Roman Lysecky , Frank Vahid, Dynamic hardware/software partitioning: a first approach, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Gaurav Mittal , David C. Zaretsky , Xiaoyong Tang , P. Banerjee, Automatic translation of software binaries onto FPGAs, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	David Zaretsky , Gaurav Mittal , Xiaoyong Tang , Prith Banerjee, Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Greg Stitt , Zhi Guo , Walid Najjar , Frank Vahid, Techniques for synthesizing binaries to an advanced register/memory structure, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, February 20-22, 2005, Monterey, California, USA
	Sankalp Kallakuri , Alex Doboli, Energy conscious online architecture adaptation for varying latency constraints in sensor network applications, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	Antonio Carlos S. Beck , Luigi Carro, Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Greg Stitt , Frank Vahid , Gordon McGregor , Brian Einloth, Hardware/software partitioning of software binaries: a case study of H.264 decode, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, September 19-21, 2005, Jersey City, NJ, USA
	M. Finc , A. Zemva, Profiling soft-core processor applications for hardware/software partitioning, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.5, p.315-329, May 2005
	Roman Lysecky , Frank Vahid , Sheldon X.-D. Tan, Dynamic FPGA routing for just-in-time FPGA compilation, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Gaurav Mittal , David Zaretsky , Gokhan Memik , Prith Banerjee, Automatic extraction of function bodies from software binaries, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Gaurav Mittal , David Zaretsky , Xiaoyong Tang , Prith Banerjee, An overview of a compiler for mapping software binaries to hardware, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.11, p.1177-1190, November 2007
	Roman Lysecky , Greg Stitt , Frank Vahid, Warp Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.11 n.3, p.659-681, July 2006
	G. Stiff , F. Vahid, New decompilation techniques for binary-level co-processor generation, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.547-554, November 06-10, 2005, San Jose, CA
	M. Singh, Memory access optimization of dynamic binary translation for reconfigurable architectures, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.1014-1020, November 06-10, 2005, San Jose, CA
	Roman Lysecky , Frank Vahid, A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, Automation and Test in Europe, p.18-23, March 07-11, 2005
	Waseem Ahmed , Doug Myers, Design Refinement for Efficient Cluste ing of Objects in Embedded Systems, Proceedings of the conference on Design, Automation and Test in Europe, p.718-719, March 07-11, 2005
	Roman Lysecky , Frank Vahid, A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, automation and test in Europe, p.10480, February 16-20, 2004
	Greg Stitt , Frank Vahid, Binary synthesis, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-30, August 2007
	Roman Lysecky , Frank Vahid, Design and implementation of a MicroBlaze-based warp processor, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.3, p.1-22, April 2009
	M. Jagadeeswari , M. C. Bhuvaneswari, Efficient multi-objective genetic algorithm for hardware-software partitioning in embedded system design: ENGA, International Journal of Computer Applications in Technology, v.36 n.3/4, p.181-190, September 2009