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On undetectable faults in partial scan circuits
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 82 - 86  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
Irith Pomeranz  Purdue University, W. Lafayette, IN
Sudhakar M. Reddy  University of Iowa, Iowa City, IA
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

We provide a definition of undetectable faults in partial scan circuits under a test application scheme where a test consists of primary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetectable under this test application scheme. We present experimental results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D. K. Pradhan and J. Saxena, "A Design for Testability Scheme to Reduce Test Application Time in Full Scan", in Proc. 10th VLSI Test Symp., April 1992, pp. 55--60.
 
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S. Y. Lee and K. K. Saluja, "Test Application Time Reduction for Sequential Circuits with Scan", IEEE Trans. on Computer-Aided Design, Sept. 1995, pp. 1128--1140.
 
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V. D. Agrawal and S. T. Chakradhar, "Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits", in Proc. 1993 Europ. Test Conf., pp. 249--253.
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V. D. Agrawal and S. T. Chakradhar, "Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits", IEEE Trans. on Computer-Aided Design, Sept. 1995., pp. 1155--1160.
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I. Pomeranz and S. M. Reddy, "On Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits", 12th VLSI Test Symp., April 1994, pp. 8--14.
 
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M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.

Collaborative Colleagues:
Irith Pomeranz: colleagues
Sudhakar M. Reddy: colleagues