| On undetectable faults in partial scan circuits |
| Full text |
Pdf
(64 KB)
|
| Source
|
International Conference on Computer Aided Design
archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
table of contents
San Jose, California
Pages: 82 - 86
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 7, Citation Count: 0
|
|
|
ABSTRACT
We provide a definition of undetectable faults in partial scan circuits under a test application scheme where a test consists of primary input vectors applied at-speed between scan operations. We also provide sufficient conditions for a fault to be undetectable under this test application scheme. We present experimental results on finite-state machine benchmarks to demonstrate the effectiveness of these conditions in identifying undetectable faults.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
D. K. Pradhan and J. Saxena, "A Design for Testability Scheme to Reduce Test Application Time in Full Scan", in Proc. 10th VLSI Test Symp., April 1992, pp. 55--60.
|
| |
2
|
|
| |
3
|
S. Y. Lee and K. K. Saluja, "Test Application Time Reduction for Sequential Circuits with Scan", IEEE Trans. on Computer-Aided Design, Sept. 1995, pp. 1128--1140.
|
| |
4
|
|
 |
5
|
|
| |
6
|
V. D. Agrawal and S. T. Chakradhar, "Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits", in Proc. 1993 Europ. Test Conf., pp. 249--253.
|
 |
7
|
|
| |
8
|
|
| |
9
|
|
| |
10
|
V. D. Agrawal and S. T. Chakradhar, "Combinational ATPG Theorems for Identifying Untestable Faults in Sequential Circuits", IEEE Trans. on Computer-Aided Design, Sept. 1995., pp. 1155--1160.
|
 |
11
|
Mahesh A. Iyer , David E. Long , Miron Abramovici, Identifying sequential redundancies without search, Proceedings of the 33rd annual conference on Design automation, p.457-462, June 03-07, 1996, Las Vegas, Nevada, United States
[doi> 10.1145/240518.240605]
|
| |
12
|
|
| |
13
|
I. Pomeranz and S. M. Reddy, "On Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits", 12th VLSI Test Symp., April 1994, pp. 8--14.
|
| |
14
|
|
| |
15
|
|
| |
16
|
M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, 1990.
|
|