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ABSTRACT
In this paper, we present several novel techniques that make the recently published multilevel routing scheme [19] more effective and complete. Our contributions include: (1) resource reservation for local nets during the coarsening process, (2) congestion-driven, graph-based Steiner tree construction during the initial routing and the refinement process and (3) multi-iteration refinement considering the congestion history. The experiments show that each of these techniques helps to improve the completion rate considerately. Compared to [19], the new routing system reduces the number of failed nets by 2× to 18×, with less than 50% increase in runtime in most cases.
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CITED BY 18
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Hsun-Cheng Lee , Yao-Wen Chang , Jer-Ming Hsu , Hannah H. Yang, Multilevel floorplanning/placement for large-scale modules using B*-trees, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
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Hailong Yao , Yici Cai , Xianlong Hong , Qiang Zhou, Improved multilevel routing with redundant via placement for yield and reliability, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
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Katherine Shu-Min Li , Chung-Len Lee , Yao-Wen Chang , Chauchin Su , Jwu-E Chen, Multilevel full-chip routing with testability and yield enhancement, Proceedings of the 2005 international workshop on System level interconnect prediction, April 02-03, 2005, San Francisco, California, USA
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Tsung-Yi Ho , Chen-Feng Chang , Yao-Wen Chang , Sao-Jie Chen, Multilevel full-chip routing for the X-based architecture, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
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