Methods for true power minimization

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Methods for true power minimization

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International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California

Pages: 35 - 42

Year of Publication: 2002

ISBN ~ ISSN:1092-3152 , 0-7803-7607-2

Authors

Robert W. Brodersen	University of California, Berkeley
Mark A. Horowitz	Stanford University
Dejan Markovic	University of California, Berkeley
Borivoje Nikolic	University of California, Berkeley
Vladimir Stojanovic	Stanford University

Sponsors

: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 17, Downloads (12 Months): 95, Citation Count: 17

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents methods for efficient power minimization at circuit and micro-architectural levels. The potential energy savings are strongly related to the energy profile of a circuit. These savings are obtained by using gate sizing, supply voltage, and threshold voltage optimization, to minimize energy consumption subject to a delay constraint. The true power minimization is achieved when the energy reduction potentials of all tuning variables are balanced. We derive the sensitivity of energy to delay for each of the tuning variables connecting its energy saving potential to the physical properties of the circuit. This helps to develop understanding of optimization performance and identify the most efficient techniques for energy reduction. The optimizations are applied to some examples that span typical circuit topologies including inverter chains, SRAM decoders, and adders. At a delay of 20% larger than the minimum, energy savings of 40% to 70% are possible, indicating that achieving peak performance is expensive in terms of energy. Energy savings of about 50% can be achieved without delay penalty with the balancing of sizes, supplies, and thresholds.

REFERENCES

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CITED BY 17

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	David Nguyen , Abhijit Davare , Michael Orshansky , David Chinnery , Brandon Thompson , Kurt Keutzer, Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Fei Li , Yan Lin , Lei He , Jason Cong, Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics, Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, February 22-24, 2004, Monterey, California, USA
	W. Hung , Y. Xie , N. Vijaykrishnan , M. Kandemir , M. J. Irwin , Y. Tsai, Total power optimization through simultaneously multiple-v_DD multiple-v_TH assignment and device sizing with stack forcing, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Yan Lin , Fei Li , Lei He, Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	Fei Li , Yan Lin , Lei He, FPGA power reduction using configurable dual-Vdd, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Fujio Ishihara , Farhana Sheikh , Borivoje Nikolić, Level conversion for dual-supply systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.185-195, February 2004
	Venkata Syam P. Rapaka , Emil Talpes , Diana Marculescu, Mixed-clock issue queue design for energy aware, high-performance cores, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.380-383, January 27-30, 2004, Yokohama, Japan
	Michael Liu , Wei-Shen Wang , Michael Orshansky, Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Benton H. Calhoun , Anantha Chandrakasan, Characterizing and modeling minimum energy operation for subthreshold circuits, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Murari Mani , Anirudh Devgan , Michael Orshansky, An efficient algorithm for statistical minimization of total power under timing yield constraints, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Yan Zhang , Sudhanva Gurumurthi , Mircea R Stan, SODA: sensitivity based optimization of disk architecture, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Joonsoo Kim , Michael Orshansky, Towards formal probabilistic power-performance design space exploration, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA
	Fei Li , Yan Lin , Lei He, Vdd programmability to reduce FPGA interconnect power, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.760-765, November 07-11, 2004
	Emil Talpes , Diana Marculescu, Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines, ACM SIGARCH Computer Architecture News, v.33 n.2, p.310-321, May 2005
	Ashish K. Singh , Michael Orshansky, Logic synthesis for reducing leakage power consumption under workload uncertainty, Proceedings of the 12th WSEAS international conference on Circuits, p.351-355, July 22-24, 2008, Heraklion, Greece
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