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Theoretical and practical validation of combined BEM/FEM substrate resistance modeling
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Source International Conference on Computer Aided Design archive
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design table of contents
San Jose, California
Pages: 10 - 15  
Year of Publication: 2002
ISBN ~ ISSN:1092-3152 , 0-7803-7607-2
Authors
E. Schrik  Delft University of Technology, DIMES, Circuits and Systems Group Mekelweg 4, Delft, The Netherlands
P. M. Dewilde  Delft University of Technology, DIMES, Circuits and Systems Group Mekelweg 4, Delft, The Netherlands
N. P. van der Meijs  Delft University of Technology, DIMES, Circuits and Systems Group Mekelweg 4, Delft, The Netherlands
Sponsors
: IEEE Circuits & Systems Society
IEEE-CS\DATC : IEEE Computer Society
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

In mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. As such, accurately modeling the properties of the substrate as a noise-propagator is becoming ever more important. A model can be obtained through the Finite Element Method (FEM) or the Boundary Element Method (BEM). The FEM performs a full 3D discretization of the substrate, which makes this method very accurate and flexible but also slow. The BEM only discretizes the contact areas on the boundary of the substrate, which makes it less flexible, but significantly faster. A combination between BEM and FEM can be efficient when we need flexibility and speed at the same time. This paper briefly describes the BEM and the FEM and their combination, but mainly concentrates on the theoretical validation of the combined method and the experimental verification through implementation in the SPACE layout to circuit extractor and comparison with commercial BEM and FEM tools.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. Gharpurey and R.G. Meyer, "Modeling and Analysis of Substrate Coupling in Integrated Circuits," IEEE Journal of Solid-State Circuits, vol. 31, pp. 344--353, Mar. 1996.
 
2
 
3
R. Singh, "A Review of Substrate Coupling Issues and Modeling Strategies," in Proc. CICC, pp. 491--498, May 1999.
 
4
F.J.R. Clement, E. Zysman, M. Kayal, and M. Declercq, "LAYIN: Toward a global solution for parasitic coupling modeling and visualization," in Proc. IEEE Custom Integrated Circuits Conference, pp. 537--540, May 1994.
 
5
 
6
X. Aragones, J.L. Gonzalez, and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Boston: Kluwer Academic Publishers, 1999.
 
7
P. Miliozzi, L. Carloni, E. Charbon, and A. Sangiovanni-Vincentelli, "SubWave: a Methodology for Modeling Digital Substrate Noise in Mixed-Signal IC's." Proceedings IEEE CICC, pp. 385--388, 1996.
 
8
M. Pfost, H.M. Rein, and T. Holzwarth, "Modeling Substrate Effects in the Design of High-Speed Si-Bipolar IC's." IEEE Journal on Solid-State Circuits, vol. 31, pp. 1493--1501, Oct. 1996.
 
9
D.K. Su, M.J. Loinaz, S. Masui, and B.A. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits," IEEE Journal of Solid-State Electronics, vol. 28, pp. 420--430, Apr. 1993.
 
10
11
 
12
G. Strang and G.J. Fix, An Analysis of the Finite Element Method. Englewood Cliffs: Prentice-Hall, Inc., 1973.
 
13
J.E. Hall, D.E. Hocevar, P. Yang, and M.M. McGraw, "SPIDER - A CAD System for Modeling VLSI Metallization Patterns," IEEE Transactions on CAD, vol. 6, pp. 1023--1031, Nov. 1987.
 
14
C.A. Brebbia, The Boundary Element Method for Engineers. Plymouth: Pentech Press, 1978.
 
15
 
16
E. B. Nowacka and N. P. van der Meijs, "The Hybrid Element Method for Capacitance Extraction in a VLSI Layout Verification System," in Software for Electrical Engineering Analysis and Design (Proc. ELECTROSOFT '96) (P.P. Silvester, ed.), (Pisa, Italy), pp. 125--134, Computational Mechanics Publications, May 1996.
 
17
E. B. Nowacka, P. Dewilde, and T. Smedes, "A Hybrid Element Method for Calculation of Capacitances from the Layout of Integrated Circuits," in Boundary Element Technology XI (Proc BETECH 96) (R. C. Ertekin, C. A. Brebbia, M. Tanak, and R. Shaw, eds.), (Hawai, U.S.A.), pp. 415--425, Computational Mechanics Publications, May 1996.
 
18
F. Beeftink, A.J. van Genderen, N.P. van der Meijs, and J. Poltz, "Deep-Submicron ULSI Parasitics Extraction Using Space," in Design, Automation and Test in Europe Conference 1998, Designer Track, pp. 81--86, Feb. 1998.
 
19
Momentum, a 2.5 D EM Simulator by Agilent EEsof, see http://eesof.tm.agilent.com.
 
20
Davinci (Taurus), a 3D Device simulator by Synopsys, see http://www.synopsys.com.


Collaborative Colleagues:
E. Schrik: colleagues
P. M. Dewilde: colleagues
N. P. van der Meijs: colleagues