Indirect VLIW memory allocation for the ManArray multiprocessor DSP

ABSTRACT

The indirect very long instruction word (iVLIW) architecture and its implementation on the BOPS ManArray family of multiprocessor digital signal processors (DSP) provides a scalable alternative to the wide instruction busses usually required in a multiprocessor VLIW DSP. The ManArray processors indirectly access VLIWs from small caches of VLIWs localized in each processing element. With this work, we present an algorithm to perform 1) iVLIW instruction memory allocation on multiple processing elements to minimize instruction memory requirements and 2) scheduling of the iVLIW setup instructions to minimize execution overhead. We present preliminary experimental results that demonstrate the effectiveness of our approach.

REFERENCES

• 1: Joseph A. Fisher, Very Long Instruction Word architectures and the ELI-512, Proceedings of the 10th annual international symposium on Computer architecture, p.140-150, June 13-17, 1983, Stockholm, Sweden
• 2: Jeff Bier, ""VLIW Architectures for DSP: A Two-Part Lecture Outline"," in International Conference on Signal Processing Applications and Techniques, Orlando, FL, 1999.
• 3: Edwin F. Barry and Gerald G. Pechanek, "Methods and apparatus for instruction addressing in indirect VLIW processors," US Patent 6,356,994, March 12 2002.
• 4: David Callahan , Ken Kennedy , Allan Porterfield, Software prefetching, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.40-52, April 08-11, 1991, Santa Clara, California, United States
• 5: Gerald G. Pechanek , Stamatis Vassiliadis , Nikos Pitsianis, ManArray Processor Interconnection Network: An Introduction, Proceedings of the 5th International Euro-Par Conference on Parallel Processing, p.761-765, August 31-September 03, 1999
• 6: Gerald G. Pechanek and Stamatis Vassiliadis, "The ManArray Embedded Processor Architecture" in Proceedings of the 26-th Euromicro Conference: "lnformatics: inventing the future", Maastricht, The Netherlands, September 5--7 2000, vol. I, pp. 348--355.
• 7: Nikos P. Pitsianis and Gerald G. Pechanek, "High-performance FFT implementation on the BOPS ManArray parallel DSP" in Advanced Signal Processing Algorithms, Architectures and Implementations IX, SPIE International Symposium, July 1999, vol. 3807, pp. 164--171.
• 8: Andrew W. Appel, Modern compiler implementation in ML: basic techniques, Cambridge University Press, New York, NY, 1997
• 9: G. J. Chaitin, Register allocation & spilling via graph coloring, Proceedings of the 1982 SIGPLAN symposium on Compiler construction, p.98-105, June 23-25, 1982, Boston, Massachusetts, United States
• 10: Alan R. Weiss, Benchmarking, Selection and Debugging of Microcontrollers, Proceedings of the 1999 IEEE International Conference on Computer Design, p.492, October 10-13, 1999
• 11: Markus Levy, "Processor benchmarks for key embedded applications" Embedded Systems Design, pp. 55--56, May 2001.
• 12: "ITU-T Recommendation G.729, CS-ACELPD," March 1996.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Microprocessors and microcomputers

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Memory technologies
  B.8 Performance and Reliability
      B.8.2 Performance Analysis and Design Aids

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Signal processing

General Terms:
Algorithms, Design, Documentation, Theory