A dual band CMOS VCO with a balanced duty cycle buffer

ABSTRACT

This paper proposes a dual band VCO with a standard 0.35? CMOS process to generate 1.07GHz and 2.06GHz. The proposed VCO architecture with 50% duty cycle circuit and a half adder(HA) is able to produce a frequency two times higher than that of the conventional VCOs. The measurement results demonstrate that the gain of VCO and power dissipation are 561MHz/V and 14.6mW, respectively. The phase noises of the dual band VCO are measured to be -99.05dBc/Hz and -94.9dBc/Hz at 2MHz offset from 1.07GHz and 2.06GHz.

REFERENCES

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• 2: Y.K.Moon, K.S.Yoon, "A 3.3V CMOS PLL with a self-Feedback VCO",IEICE Transaction on Fundamentals, vol.E83-A, No.12, pp2623--pp2626, Dec.2000.
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INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Measurement

Keywords:
VCO, dual band