54x54-bit radix-4 multiplier based on modified booth algorithm

ABSTRACT

In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 28-2, 27-2, ..., and 10-2 compressors, and XOR based adder are proposed. While the whole design is coded in Verilog-HDL language and implemented through commercially available EDA tool chain, the implementation gives comparable results to full custom designs [1][2]. Realistic simulations using extracted timing parameters from the layout show that the propagation time of a critical path is 3.25ns at 2.5V on a 0.18um process technology, which is almost 21% faster than the conventional multiplier [2].

REFERENCES

• 1: N. Ohkubo, et al., "A 4.4ns CMOS 54x54-b Multiplier Using Pass -Transistor Multiplexer", IEEE J. of Solid-State Cir- cuits, vol. 30, no. 3, pp. 251--257, Mar., 1995.
• 2: G. Goto, et al., "A 4.1-ns Compact 54--54-b Multiplier Utilizing Sign-Select Booth Encoders", IEEE J. of Solid-state Circuits, vol. 32, no. 11, pp. 1676--1681, Nov. 1997.
• 3: Anantha P. Chandrakasan , Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Norwell, MA, 1995
• 4: Joseph J. F. Cavanagh, Digital Computer Arithmetic, McGraw-Hill, Inc., New York, NY, 1983
• 5: K. Yano, et al., "A 3.8-ns CMOS 16x16-bit Multiplier Using Compl- ementary Pass-transistor Logic", IEEE J. of Solid-State Circuits, vol. 25, no. 2, pp. 388--395, Apr., 1990.
• 6: R. Zimmermmann, et al., "Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic", IEEE J. of Solid- state Circuits, vol. 32, no. 7, pp. 1079--1090, July, 1997.
• 7: Verilog-HDL by Cadence co., ltd.
• 8: Chip Synthesis by Synopsys co., ltd.
• 9: Hagihara. Y, et al., "A 2.7ns 0.25um CMOS 54x54 b multiplier", Solid-State Circuits Conference, 1998, Digest of Technical papers, 45th ISSCC 1998 IEEE International, pp. 296--297, 5-7 Feb 1998.
• 10: O. L. McSorley, "High Speed Arithmetic in Binary Computers", Proc. IRE, Vol 49, pp 67--71, Jan. 1961
• 11: Electrical and computer Engineering, Oklahoma state university. http://ee.okstate.edu/Courses/Descriptions/6263.htm.
• 12: Gustavo a. Ruiz, "Evaluation of three 32-bit CMOS adders in DCVS Logic for Self-Timed Circuits", IEEE IEEE J. of Solid-State Circuits, Vol.33, no.4, pp.604--613, April, 1998.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Algorithms implemented in hardware; Microprocessors and microcomputers

General Terms:
Algorithms, Design, Performance

Keywords:
adder, booth encoder, compressor, multiplier, wallace tree