| 3D direct vertical interconnect microprocessors test vehicle |
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Great Lakes Symposium on VLSI
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Proceedings of the 13th ACM Great Lakes symposium on VLSI
table of contents
Washington, D. C., USA
Session: VLSI design
table of contents
Pages: 141 - 146
Year of Publication: 2003
ISBN:1-58113-677-3
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Authors
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John Mayega
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Rensselaer Polytechnic Institute, Troy, NY
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Okan Erdogan
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Rensselaer Polytechnic Institute, Troy, NY
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Paul M. Belemjian
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Rensselaer Polytechnic Institute, Troy, NY
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Kuan Zhou
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Rensselaer Polytechnic Institute, Troy, NY
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John F. McDonald
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Rensselaer Polytechnic Institute, Troy, NY
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Russel P. Kraft
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Rensselaer Polytechnic Institute, Troy, NY
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| Bibliometrics |
Downloads (6 Weeks): 3, Downloads (12 Months): 42, Citation Count: 5
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ABSTRACT
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated Circuits (IC) such as microprocessors have been entering the giga-hertz operating frequency range, various speed related roadblocks have become increasingly difficult to overcome. The migration to smaller devices has raised serious challenges. The major impediment to fulfill Moore's Law effectively in the years to come is increasingly becoming the interconnect. ICs are using a greater fraction of their clock cycles charging interconnect wires. IC interconnect related speed degradation has stimulated much research effort in the area of low dielectric constant materials. A relatively novel approach, wafer scale 3-dimensional (3D) integration attempts to by-pass the large wire parasitics by shortening wires. This paper is going to elaborate on a 3D microprocessor test vehicle. We intend to demonstrate the speed advantages, which may be derived from 3D integration, through a combination of fabrication, testing and simulation.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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The Interconnect chapter in the 2001 International Technology Roadmap for Semiconductors, pp 20.
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R.J. Gutmann, J.-Q. Lu, Y. Kwon, J.F. McDonald, T.S. Cale, "Three-dimensional (3D) ICs: A Technology Platform for Integrated Systems and Opportunities for New Polymeric Adhesives", First International Conference on Polymers and Adhesives in Microelectronics and Photonics, 2001.
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J. Kalyanasundharam, R.B. Iverson, "Application of a global-local random-walk algorithm for thermal analysis of 3D integrated circuits", Advanced Metallization Conference, Oct 2002.
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George R, Wilson, "Advances in bipolar" VLSI Proceedings of the IEEE, Volume: 78 Issue: 11, pp.1707--1719. Nov. 1990.
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John F. McDonald; Russell P. Kraft, "A Theory for Detection and Mitigation for SiGe HBT Full Differential CML SEU Faults", NASA 10th Symposium, March, 2002.
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Don Draper, "AmberWave Commercializes Strained Silicon", Microprocessor: The Insider's Guide to Microprocessor Hardware, April 22, 2002.
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David L, Harame; Bernard S, Meyerson, "The Early History of IBM's SiGe Mixed Signal Technology", IEEE Transaction on Electron Devices, Volume: 48 Issue: 11, pp. 2555--2567, Nov 2001.
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Crabbe, E.; Meyerson, B.; Harame, D.; Stork, J.; Megdanis, A.; Cotte, J.; Chu, J.; Gilbert, M.; Stanis, C.; Comfort, J.; Patton, G.; Subbanna, S. "113-GHz f/sub T/ graded-base SiGe HBT's", IEEE Transactions on Electron Devices, Volume: 40 Issue: 11, pp. 2100--2101Nov. 1993.
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10
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CITED BY 5
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Bryan Black , Murali Annavaram , Ned Brekelbaum , John DeVale , Lei Jiang , Gabriel H. Loh , Don McCaule , Pat Morrow , Donald W. Nelson , Daniel Pantuso , Paul Reed , Jeff Rupley , Sadasivan Shankar , John Shen , Clair Webb, Die Stacking (3D) Microarchitecture, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.469-479, December 09-13, 2006
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INDEX TERMS
Primary Classification:
B.
Hardware
B.7
INTEGRATED CIRCUITS
B.7.1
Types and Design Styles
Additional Classification:
B.
Hardware
B.8
Performance and Reliability
B.8.0
General
General Terms:
Design,
Experimentation,
Performance,
Verification
Keywords:
3D integration,
SiGe HBT,
adder,
current mode logic,
direct vertical integration,
finite state machine,
interconnect,
microprocessor,
register file
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