A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology

ABSTRACT

A high speed, low power FPGA design is presented in this paper. This gigahertz FPGA design has an improved XC6200 structure. Redundant multiplexers are eliminated from critical signal path to enhance the performance of the previous design. By balancing between the power consumption and performance, the simulated clock rate is from 5 GHz to 20 GHz and the power consumption is from 4 mW to 12 mW per single cell in the IBM 7HP SiGe HBT BiCMOS process.

REFERENCES

• 1: John F. McDonald , Bryan S. Goda, Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS, Proceedings of the 1st NASA/DOD workshop on Evolvable Hardware, p.188, July 19-21, 1999
• 2: Bryan S. Goda, John F. McDonald, Stephen R. Carlough, Thomas W. Krawczyk Jr. and Russell P. Kraft, "SiGe HBT BiCMOS FPGAs for fast reconfigurable computing," IEE Proc.-Compu. Digi. Tech, vol.147, no. 3 pp. 189--194.
• 3: "IBM SiGe Designer's manual", (IBM Inc. Burlington Vermont. 2001).
• 4: Harme, D., Crabbe, E., Cressler, J., Comfort, J., Sun, J., Stiffler, S., Kobeda, E., Burghartz, M., Gilbert, J., Malinowski, A., Dally, S.,Rathanphanyarat, M., Saccamango, W., Cotte, J., Chu, C., Stork,J.: "A High Performance Epitaxial SiGe-Base ECL BiCMOS Technology," IEEE IEDMTech Digest, 1992, PP. 2.1.1--2.1.4.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Gate arrays

General Terms:
Design

Keywords:
BC, BCII, CML, FPGA, dynamic routing