Some results in memory conflict analysis

ABSTRACT

The delay of accesses in shared-memory vector multiprocessors is considered. Simple formulae are presented which predict the delays of both scalar and vector accesses with a variety of loads in terms of memory technology and design parameters. Comparisons are made with both simulated and measured results on five CRAY memory systems.

REFERENCES

• 1: Chang, D. Y., D. J. Kuck, and D. H, Lawrie, "On the Effective Bandwidth of Parallel Memories," Trans. IEEE, Vol. C-26, No. 5, (May 1977), pp 480-489.
• 2: David H. Bailey, Vector computer memory bank contention, IEEE Transactions on Computers, v.36 n.3, p.293-298, March 1987 [doi>10.1109/TC.1987.1676901]
• 3: Tony Cheung , James E. Smith, A simulation study of the CRAY X-MP memory system, IEEE Transactions on Computers, v.35 n.7, p.613-622, July 1986 [doi>10.1109/TC.1986.1676802]
• 4: D. A. Calahan, An Analysis of Vector Startup Access Delays, IEEE Transactions on Computers, v.37 n.9, p.1134-1137, September 1988 [doi>10.1109/12.2266]
• 5: Calahan, D. A., "Characterization of Memory Conflict Loading on the Cray-2," Proc. 1988 Intl. Conf. on Parallel Processing, St. Charles, Ill, August, 1988.
• 6: Fannes, G.J., and J.L. Schwttrzmeier, "Comparing the Performance of CRAY Y-MP and CRAY X-MP Computer Systems," Cray Channels, Winter 1'989, pp 26-30.

INDEX TERMS

Primary Classification:
  D. Software
  D.4 OPERATING SYSTEMS
      D.4.2 Storage Management
          Subjects: Distributed memories

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Shared memory

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES

  I. Computing Methodologies
  I.6 SIMULATION AND MODELING

General Terms:
Algorithms, Design, Experimentation, Performance