Communication in iWarp systems

ABSTRACT

The iWarp processor is a building block for parallel systems and is developed in a joint project by Carnegie Mellon University and Intel Corporation. The iWarp processor integrates computation and communication: the iWarp component architecture consists of a computation agent, capable of delivering 20 MFLOPS and 20 MIPS, and a communication agent that provides a bandwidth of 320 MBytes/sec. We expect the first iWarp-based system to be available early 1990, organized as a 8X8 two-dimensional torus. Fast inter-processor communication is crucial for the success of a parallel system, and this paper describes communication in iWarp systems. We review the communication models, message passing and systolic communication, that this architecture aims to support and introduce the types of networks that can be realized by the iWarp communication agent. We also sketch a programmer interface to these networks and give usage examples for iWarp networks.

REFERENCES

• 1: M. Annaratone , E. Arnould , T. Gross , H. T. Kung , M. Lam, The warp computer: Architecture, implementation, and performance, IEEE Transactions on Computers, v.36 n.12, p.1523-1538, Dec. 1987 [doi>10.1109/TC.1987.5009502]
• 2: Emmanuel Arnould , H. T. Kung , Francois Bitz , Robert D. Sansom , Eric C. Cooperm, The design of nectar: a network backplane for heterogeneous multicomputers, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.205-216, April 03-06, 1989, Boston, Massachusetts, United States
• 3: S. Borkar , R. Cohn , G. Cox , S. Gleason , T. Gross, Warp: an integrated solution of high-speed parallel computing, Proceedings of the 1988 ACM/IEEE conference on Supercomputing, p.330-339, November 12-17, 1988, Orlando, Florida, United States
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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Parallel processors**

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

  F. Theory of Computation
  F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
      F.2.2 Nonnumerical Algorithms and Problems
          Subjects: Routing and layout

General Terms:
Algorithms, Design, Performance