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Design methodology and microdiagnostics development for a self-checking microprocessor
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Source International Symposium on Microarchitecture archive
Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture table of contents
Dublin, Ireland
Pages: 70 - 82  
Year of Publication: 1989
ISBN:0-89791-324-8
Also published in ...
Authors
R. A. Parekhji  Computer Science & Engineering Department, Indian Institute of Technology, Bombay 400076, India
N. K. Nanda  Division of Computer Science, Asian Institute of Technology, P.O. Box 2754. Bangkok 10501, Thailand
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

The conventional design of electronic circuits is intolerant to operational faults. Self-checking logic is aimed at online fault detection and can hence be incorporated to achieve reliable operation. In this paper, the design of a self-checking microprocessor is discussed. Self-checking strategies for different functional units are selectively and judiciously applied, and also modified wherever necessary, for the design of the register section, the arithmetic & logic unit and the control unit. A self-checking microprogrammed control unit, capable of supporting normal instruction execution concurrently with diagnostics, is developed. The design methodology has been applied to Intel's 8085A microprocessor as a case study to make it self-testing. Overheads involved have also been estimated.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
D.A. Rennels, ' Fault. Toterant Computing - Concepts b Examples', IEEE Trans. Computers, Vol. C-33, No. 12, Oecember 1984, PP. 1116-1129.
 
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3
S.M. Thatte b J.A. Abraham, 'Test Generation for Microprocessors ' , IEEE Trans. Computer, Vol. c-29, No. 6, June 1980. pp. 430-441.
 
4
 
5
M.P. lialbert b S.M. Bose, 'Design approach for a VLSI Self-Checking MIL-.STO-.1750A Microprocessor', Proc. 14th Int. Symp. on Fault-Tolerant Computing, IEEE-CS Press, June 1984, pp. 254-253.
 
6
F. Somenzi t G. Silvano. 'Fault Detection in Programmable Logic Arrays', Proc. IEEE, Vol. 74. No. 5, May 1986, pp. 655-668.
 
7
M. Nicolaidis, 'Evaluation of a Self-Checking Version of the MC68000 Microprocessor', Proc. 15th Int. Symp. on Fault-Toterant Computing, IEEE- CS Press, June 1985, pp. 350-356.
 
8
Y. Crouzet ~ C. Landrault, 'Design of Self-Checking MOS-LSI Circuits: application to a Four.- Bit Microprocessor', IEEE Trans. Computers, Vol. C-23, No. 6, June 1980, pp. 532-537.
 
9
R.W. Goody, THE INTELLIGENT MICROCOMPUTER, Science Research Associates, Inc., 1982.
 
10
R.A. Parekhji, 'Design Methodology for a Self-Checking Microprocessor', M. Tech. Dissertation, University Of Roorkee, Roorkee, India, February 1988.
 
11
T. Nanya b T. Kawamura, ' Error Secure/Propagating Concept and Its Application to the Design of Strongly Fault-Secure Processors, Proc. 15th Int. Symp. on Fault-toterant Computing, IEEE-CS Press, June 1985, pp. 396-401.

Collaborative Colleagues:
R. A. Parekhji: colleagues
N. K. Nanda: colleagues