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“Combining” as a compilation technique for VLIW architectures
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Source International Symposium on Microarchitecture archive
Proceedings of the 22nd annual workshop on Microprogramming and microarchitecture table of contents
Dublin, Ireland
Pages: 43 - 55  
Year of Publication: 1989
ISBN:0-89791-324-8
Also published in ...
Authors
T. Nakatani  IBM Tokyo Research Laboratory, 5-19 Sanbancho, Chiyoda-ku, Tokyo
K. Ebcioğlu  IBM Thomas J. Watson Research Center, P.O.Box 218, Yorktown Heights, NY
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 5,   Downloads (12 Months): 25,   Citation Count: 16
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ABSTRACT

Combining is a local compiler optimization technique that can enhance the performance of global compaction techniques for VLIW machines. Given two adjacent operations of a certain class that are flow (read-after-write) dependent and that cannot be placed in the same micro-instruction, the combining technique can transform the operations so that the modified operations have no dependence. The transformed operations can be executed in the same micro-instruction, thus allowing the total execution time of the program to be reduced. In this paper, combining a pair of flow-dependent operations into a wide instruction word is suggested as an important compilation technique for VLIW architectures. Combining is particularly effective with software pipelining and loop unrolling since combinable operations can come together with a higher probability when these compilation techniques are used. We implemented combining in our parallelizing compiler for the wide instruction word architecture, which is now being built at the IBM T. J. Watson Research Center. It is shown that ten percent speedup is obtained on the Stanford integer benchmarks and other sequential-matured C programs, in comparison to compaction techniques that do not use combining. For a class of inner loops, combining can remove the inter-iteration dependencies completely and can improve performance in the same ratio as the loop is unrolled.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Ebcioglu, K. {1988}. Some Design Ideas for a VLIW Architecture for Sequential Natured Software, Parallel Processing (Proceedings of IFIP WC 10.3 Working Conference on Parallel Processing), M. Cosnard et al. (eds.), pp. 1-21, North Holland.
 
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Warren, S.H., Auslandcr, M.A., Chaitin, G.J., Chibib, A.C., Hopkins, M.E., and MacKay, A.L. {1986}. Final Code G eneration in the PL.8 Compiler, Report No. RC 11974, IBM T.J. Watson Research Center.

CITED BY  16

Collaborative Colleagues:
T. Nakatani: colleagues
K. Ebcioğlu: colleagues