| DYNAJUST: an efficient automatic routing technique optimizing delay conditions |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 26th ACM/IEEE Design Automation Conference
table of contents
Las Vegas, Nevada, United States
Pages: 791 - 794
Year of Publication: 1989
ISBN:0-89791-310-8
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Authors
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Y. Fujihara
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Hitachi Research Laboratory, Hitachi Ltd., 4026 Kuji-cho, Hitachi-shi, Ibaraki-ken, 319-12, Japan
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Y. Sekiyama
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Hitachi Research Laboratory, Hitachi Ltd., 4026 Kuji-cho, Hitachi-shi, Ibaraki-ken, 319-12, Japan
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Y. Ishibashi
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Hitachi Research Laboratory, Hitachi Ltd., 4026 Kuji-cho, Hitachi-shi, Ibaraki-ken, 319-12, Japan
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M. Yanaka
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Hitachi Research Laboratory, Hitachi Ltd., 4026 Kuji-cho, Hitachi-shi, Ibaraki-ken, 319-12, Japan
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Downloads (6 Weeks): 7, Downloads (12 Months): 11, Citation Count: 4
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ABSTRACT
A new routing technique DYNAJUST, Dynamic Wire Length Adjustment, is described. It accurately realizes specified wire lengths to fulfill delay conditions. The implementation, based on the combination of shortest path algorithms, is proposed to achieve a high completion ratio in a short processing time. The technique is useful in practical situations where high accuracy is required of many nets.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
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Yasushi Ogawa , Tatsuki Ishii , Yoichi Shiraishi , Hidekazu Terai , Tokinori Kozawa , Kyoji Yuyama , Kyoji Chiba, Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.404-410, July 1986, Las Vegas, Nevada, United States
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H. Terai~ et al., "Performance Analysis of Automatic Placement and Routing for Large-Scale CHOS Mastersllces" in Proc IEEE International Conference on Computer Design~ VLSI{ in Computers (ICCD) 1983, pp. 536-539.
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S. Asahara, et al. ~ "An Analysis of Wiring Performances of a Routing System for High Density Printed Wiring Boards", IECE Trans. Vol. J65-A, pp. 159-166 (1982) (in Japanese).
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C.Y. Lee, "An Algorithm for Path Connections and Its Applications", IRE Trans. Electron. Comput., Vol. EC-10~ pp. 346-365~ 1961.
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CITED BY 4
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Jin Huang , Xian-Long Hong , Chung-Kuan Cheng , E. S. Kuh, An efficient timing-driven global routing algorithm, Proceedings of the 30th international conference on Design automation, p.596-600, June 14-18, 1993, Dallas, Texas, United States
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Hidekazu Terai , Fumio Goto , Katsuro Wakai , Tokinori Kozawa , Mitsugu Edagawa , Satoshi Hososaka , Masahiro Hashimoto, Basic concepts of timing-oriented design automation for high-performance mainframe computers, Proceedings of the 28th conference on ACM/IEEE design automation, p.193-198, June 17-22, 1991, San Francisco, California, United States
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Tong Jing , Xianlong Hong , Haiyun Bao , Yici Cai , Jingyu Xu , Chungkuan Cheng , Jun Gu, UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
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