Automatic sizing of power/ground (P/G) networks in VLSI

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Automatic sizing of power/ground (P/G) networks in VLSI

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 783 - 786

Year of Publication: 1989

ISBN:0-89791-310-8

Authors

R. Dutta	Digital Equipment Corporation, Hudson, Mass.
M. Marek-Sadowska	University of California, Berkeley, Calif.

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 7, Downloads (12 Months): 13, Citation Count: 13

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abstract references cited by index terms collaborative colleagues

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ABSTRACT

This paper presents a fast and efficient method for sizing power/ground networks. No restrictions on network topology or number of supplying pads are imposed. Wire widths are calculated such that the weighted area of wire segments is minimized while electromigration and voltage drops constraints are fulfilled. The algorithm proposed here runs 50% faster than the best methods reported for tree type network topologies.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. Chowdhury and M.A. Breuer, "Optimllm Design of IC Power/Ground Nets Subject to Reliability Constraints," IEEE Trans. on CAD of IC, pp. 787-796, June 198 7.
	2	S. Chowdhury, An automated design of minimum-area IC power/ground nets, Proceedings of the 24th ACM/IEEE conference on Design automation, p.223-229, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37927]
	3	S. Chowdhury , M. A. Breuer, Minimal area sizing of power and ground nets for VLSI circuits, Proceedings of the fourth MIT conference on Advanced research in VLSI, p.141-169, June 1986, Cambridge, Massachusetts, United States
	4	R.K. Brayton, G.D. Hachtel, A. Sangiovsnni- V'mcenteHi, "A Survey of Optimization Techniques for Integrated Circuit Design,~ Proc. oflEEE,, pp. 1334- 1362, October 1981.
	5	A. Ralston and P. Rabinowitz, First Course in Numerical Analysis, McGraw Hill Book Co. New York, NY, 1978.
	6	S.W. Director, R.A. Roher, "A Generalized Adjoint Network and Network Sensitivities," IEEE 73~ns. on Ccts. and Sys., v. CT-16, pp. 330-336, August 1969.
	7	W. Dai, H.H. Chen, R. Dutts, M. Jac~mon, E.S. Kuh, M. Marek-Sadowska, M. Sato, D. Wang and X. Xiong, "BEAR: A New Building Block L~,yout Sysre.m," Proc. of ICCAD, 1987, pp. 34-37.

CITED BY 13

	T. Mitsuhashi , E. S. Kuh, Power and ground network topology optimization for cell based VLSIs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.524-529, June 08-12, 1992, Anaheim, California, United States
	Jaewon Oh , Massoud Pedram, Multi-pad power/ground network design for uniform distribution of ground bounce, Proceedings of the 35th annual conference on Design automation, p.287-290, June 15-19, 1998, San Francisco, California, United States
	X.-D. Sheldon Tan , C.-J. Richard Shi, Fast power/ground network optimization based on equivalent circuit modeling, Proceedings of the 38th conference on Design automation, p.550-554, June 2001, Las Vegas, Nevada, United States
	Xiang-Dong Tan , C.-J. Richard Shi , Dragos Lungeanu , Jyh-Chwen Lee , Li-Pen Yuan, Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings, Proceedings of the 36th ACM/IEEE conference on Design automation, p.78-83, June 21-25, 1999, New Orleans, Louisiana, United States
	Shiyou Zhao , Kaushik Roy , Cheng-Kok Koh, Decoupling capacitance allocation for power supply noise suppression, Proceedings of the 2001 international symposium on Physical design, p.66-71, April 01-04, 2001, Sonoma, California, United States
	Kai Wang , Malgorzata Marek-Sadowska, On-chip power supply network optimization using multigrid-based technique, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Davide Bertozzi , Luca Benini , Giovanni De Micheli, Energy-reliability trade-off for NoCs, Networks on chip, Kluwer Academic Publishers, Hingham, MA, 2003
	Su-Wei Wu , Yao-Wen Chang, Efficient power/ground network analysis for power integrity-driven design methodology, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Aman A. Kokrady , C. P. Ravikumar, Static Verification of Test Vectors for IR Drop Failure, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.760, November 09-13, 2003
	Shuai Li , Jin Shi , Yici Cai , Xianlong Hong, Vertical via design techniques for multi-layered P/G networks, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	Shiyou Zhao , Kaushik oy , Cheng-Kok Koh, Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.489, January 07-11, 2002
	Ting-Yuan Wang , Jeng-Liang Tsai , Charlie Chung-Ping Chen, Thermal and Power Integrity Based Power/Ground Networks Optimization, Proceedings of the conference on Design, automation and test in Europe, p.20830, February 16-20, 2004
	Chao-Hung Lu , Hung-Ming Chen , Chien-Nan Jimmy Liu, Effective decap insertion in area-array SoC floorplan design, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.4, p.1-20, September 2008