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A comparison of four two-dimensional gate matrix layout tools
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents
Las Vegas, Nevada, United States
Pages: 698 - 701  
Year of Publication: 1989
ISBN:0-89791-310-8
Authors
M. J. Irwin  Department of Computer Science, The Pennsylvania State University, University Park, PA
R. M. Owens  Department of Computer Science, The Pennsylvania State University, University Park, PA
Sponsors
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 6,   Citation Count: 3
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ABSTRACT

A comparison of four layout tools is presented. The layout style is a two-dimensional gate matrix. The first layout tool discussed uses “standard” simulated annealing. Annealing on gate clusters instead of individual gates can be used to improve the layout results. Two different ways of determining good gate clusters for use in the annealing process are compared. The first way uses clusters derived from user specified gate hierarchies, while the second determines clusters based on gate connectivity. The fourth layout tool uses a decomposition scheme based on quadrisection. Layout results for a set of benchmark circuits are presented for each of the tools.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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OwI
Owens, R.M. and M.J. Irwin, Clustering Based Simulated Annealing Sea-of-Transistor Layout Tools, CS- 88-09, PSU, also submitted to IEEE Trans on CAD.
 
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Suaris, P. and G. Kedem, Quadrisection: A New Approach to Standard Cell Layout, Proc of ICCAD, Nov 1987.
 
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Collaborative Colleagues:
M. J. Irwin: colleagues
R. M. Owens: colleagues