An efficient finite element method for submicron IC capacitance extraction

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An efficient finite element method for submicron IC capacitance extraction

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 26th ACM/IEEE Design Automation Conference table of contents

Las Vegas, Nevada, United States

Pages: 678 - 681

Year of Publication: 1989

ISBN:0-89791-310-8

Authors

N. P. van der Meijs	Delft University of Technology, Department of Electrical Engineering, Mekelweg 4, 2628 CD Delft, The Netherlands
A. J. van Genderen	Delft University of Technology, Department of Electrical Engineering, Mekelweg 4, 2628 CD Delft, The Netherlands

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS\TCDA : TC Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 12, Downloads (12 Months): 31, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R.L.M. Dang and N. Shigyo, "Coupling capacitances for twodimensional wires," 1EEE Electron Device Letters EDL-2(8)pp. 196-197 (Aug. 1981).
	2	W.H. Dierking and J.D. Bastian, "VLSI parasitic capacitance determination by flux tubes," IEEE Circuits and Systems Magazine, pp. 11-18 (Mar. 1982).
	3	A. Seidl, M. Svoboda, J. Obemdorfer, and W. Rosner, "CAt~AL - A 3-D Capacitance Solver for Support of CAD Systems," IEEE Trans. on CAD CAD-7(5) pp. 549-556 (May 1988).
	4	R. Guerrieri and A.L Sangiovanni-Vincentelli, "Three Dimensional Capacitance Evaluation on a Connection Machine," Proc. IEEE ICCAD.87, Santa Clara, pp. 446-449 (Nov. 9-11 1987).
	5	P. E. Cottrell , E. M. Buturla, VLSI wiring capacitance, IBM Journal of Research and Development, v.29 n.3, p.277-288, May 1985
	6	A.E. Ruehli, "Survey of computer-aided electrical analysis of integrated circuit interconnections," IBM J. Res. Develop. 23(6) pp. 626-639 (Nov. 1979).
	7	A.E. Ruehli and P.A. Brennan, "Capacitance models for integrated circuit metallization wires," IEEE Journal of Solid- State Circuits SC-10(6) pp. 530-536 (Dec. 1975).
	8	Z.Q. Ning, P.M. Dewilde, and F.L Neerhoff, "Capacitance Coefficients for VLSI Multilevel Metallization Lines," IEEE Trans. on Electron Devices ED-34(3) pp. 644-649 (March 1987).
	9	Steven P. McCormick, EXCL: A circuit extractor for IC designs, Proceedings of the 21st conference on Design automation, p.616-623, June 25-27, 1984, Albuquerque, New Mexico, United States
	10	Z.Q. Ning and P.M. Dewilde, "An Efficient Modelling Technique for Computing the Parasitic Capacitances in VLSI Circuits," Proc, ISCAS-88, pp. I131-1134 (June 1988).
	11	Z.Q. Ning and P. Dewilde, "SPIDER: Capacitance Modelling for VLSI laterconnectiotas," IEEE Trans. on Computer-Aided Design, to be published, (I 2)(December 1988).
	12	P. Dewilde , E. F. Deprettere, Approximative inversion of positive matrices with applications to modelling, Proceedings of NATO Advanced Research Workshop on Modelling, robustness and sensitivity reduction in control systems, p.211-238, May 1987, Groningen, The Netherlands
	13	H. Dym and I. Gohberg, "Extensions of band matrices with band inverses," Linear algebra and its applications, (36)(1981).
	14	H. Nelis, E. Deprettere, and P. Dewflde, "Approximate Inversion of Positive Definite Matrices, specified on a Multiple Band," Proc. SPIE 88, San Diego,(Aug. 1988).
	15	A.J. van Genderen and N.P. van der Meijs, "'Extracting Simple but Accurate RC Modds for VLSI Interconnect," Proc. ISCAS-88, Helsinki, Finland, pp. 2351-2354 (June 7-9, 1988).

CITED BY 5

	N. H. Chang , K.-J. Chang , J. Leo , K. Lee , S.-Y. Oh, IPDA: interconnect performance design assistant, Proceedings of the 29th ACM/IEEE conference on Design automation, p.472-477, June 08-12, 1992, Anaheim, California, United States
	A. J. van Genderen , N. P. van der Meijs, Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.764-769, November 07-11, 1993, Santa Clara, California, United States
	Michael W. Beattie , Lawrence T. Pileggi, Bounds for BEM capacitance extraction, Proceedings of the 34th annual conference on Design automation, p.133-136, June 09-13, 1997, Anaheim, California, United States
	Rahul Kundu , R. D. (Shawn) Blanton, ATPG for Noise-Induced Switch Failures in Domino Logic, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.765, November 09-13, 2003
	U. Geigenmüller , N. P. van der Meijs, Cartesian Multipole Based Numerical Integration for 3D Capacitance Extraction, Proceedings of the 1997 European conference on Design and Test, p.256, March 17-20, 1997