AWEsim: asymptotic waveform evaluation for timing analysis

ABSTRACT

Most timing analyzers rely upon a linear approximate interconnect model, typically an RC tree, to estimate efficiently the propagation delays for digital MOS integrated circuits. RC tree methods are adequate to analyze a large class of MOS circuits, but are not sufficient in general for high speed, dynamic and precharge MOS circuits. In addition bipolar logic and board level digital systems can have interconnect models which may not be compatible with RC tree topologies. In this paper we describe AWEsim, a variable refinement waveform estimator for generalized linear RLC approximate interconnect models.

REFERENCES

• 1: Rathin Putatunda, Auto-delay: A program for automatic calculation of delay in LSI/VLSI chips, Proceedings of the 19th conference on Design automation, p.616-621, January 1982
• 2: J.K. Ousterhout. CRYSTAL: A Timing Analyzer for NMOS VLSI Circuits. In Proc. of the 3rd Caltech Conference on VLSL pages 57-69, March 1983.
• 3: N.P. 3ouppi. TV: An nMOS Timing Analyzer. In Proc. Srd CalTech Conj. VLSI, March 1983.
• 4: J. Rubenstein, P. Penfield, Jr. and M.A. Horowitz. Signal Delay in RC Tree Networks. IEEE Tran,. on Computer Aided Design, CAD-2:202-211, 1983.
• 5: T.-M. Lin and C.A. Mead. Signal Delay in General RC Networks. IEEE Tran#. on Computer Aided Design, CAD- 3:331-349, 1984.
• 6: M.A. Horowltz. Timing Models for MOS Circuits. PhD thesis, Stanford University, January 1984.
• 7: J.L. Wyatt. Circuit Analysis, Simulation and Design, chapter Signal Propogatlon Delay in RC Models for Interconnect. North-Holland, 1987.
• 8: Seung H. Hwang , Young H. Kim , A. R. Newton, An accuration delay modeling technique for switch-level timing verification, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.227-233, July 1986, Las Vegas, Nevada, United States
• 9: L. Pillage and R. Rohrer. Asymptotic Waveform Evaluation. Technical Report CMUCAD-88-44, Semiconductor Research Corporation, October 1988.
• 10: Lawrence T. Pillage , Ronald A. Rohrer, Delay evaluation with lumped linear RLC interconnect circuit models, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.143-158, June 1989, Cambridge, Massachusetts, United States
• 11: W.C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers. J. Apl)l. Phys., 19(1):55-63, 1948.
• 12: P. O'Brien and J. Wyatt. Signal Delay in ECL Interconnect. In Proceeding8 IEEE International Symposium on Circuit~ and Systems, May 1986.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Waveform analysis

General Terms:
Algorithms, Design, Performance, Theory