A note on clustering modules for floorplanning

ABSTRACT

Many VLSI floorplanners work by recursively decomposing rectangular modules into lower-level rectangular modules until the leaf-level modules are reached[5]. Good layouts require good floorplans. The quality of a floorplan depends (among other things) on how the leaf-level modules are clustered into the various levels of the hierarchy. Some of the factors that determine the suitability of a decomposition are the geometry of the modules, the connectivity among modules, and timing constraints. Our experience with the mechanization of a VLSI design manager[1] has shown that the initial structural hierarchy that arises during synthesis from behavioral specifications is not always suitable for floorplanning. We describe hierarchical-clustering-based algorithms that lead to a small number of superior candidate hierarchies.

REFERENCES

• 1: B. D. Ackland et al., "CADRE - A System of Cooperating VLSI Design Experts," ICCD, (1985).
• 2: John A. Hartigan, Clustering Algorithms, John Wiley & Sons, Inc., New York, NY, 1975
• 3: Michael C. McFarland, Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.474-480, July 1986, Las Vegas, Nevada, United States
• 4: P, A. Subrahmanyam, "Perspectives on Specification Driven VLSI Design," A TNT Bell Labs Internal Memorandum, (1987).
• 5: M. Yu, "FORK - A floorplanning expert for custom VLSI design," pp. 34-37 in ICCD, (1987).

INDEX TERMS

Primary Classification:
  I. Computing Methodologies
  I.2 ARTIFICIAL INTELLIGENCE

General Terms:
Algorithms, Design